D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 17

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.6
6.7
6.8
6.9
6.10 Bus Release....................................................................................................................... 210
6.11 Bus Arbitration.................................................................................................................. 213
6.12 Resets and the Bus Controller ........................................................................................... 215
Section 7 DMA Controller (Not Supported in the H8S/2321) ..........................217
7.1
7.2
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation.................................................................................................... 192
6.5.11 Refresh Control.................................................................................................... 195
DMAC Single Address Mode and DRAM Interface (Not supported in the H8S/2321) ... 198
6.6.1
6.6.2
Burst ROM Interface......................................................................................................... 200
6.7.1
6.7.2
6.7.3
Idle Cycle .......................................................................................................................... 203
6.8.1
6.8.2
Write Data Buffer Function .............................................................................................. 209
6.10.1 Overview.............................................................................................................. 210
6.10.2 Operation ............................................................................................................. 210
6.10.3 Pin States in External Bus Released State............................................................ 211
6.10.4 Transition Timing ................................................................................................ 212
6.10.5 Usage Note........................................................................................................... 213
6.11.1 Overview.............................................................................................................. 213
6.11.2 Operation ............................................................................................................. 213
6.11.3 Bus Transfer Timing ............................................................................................ 214
6.11.4 External Bus Release Usage Note........................................................................ 215
Overview........................................................................................................................... 217
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode) .............................................................. 223
7.2.1
7.2.2
7.2.3
Precharge State Control ....................................................................................... 187
Wait Control ........................................................................................................ 188
Byte Access Control ............................................................................................ 190
When DDS = 1..................................................................................................... 198
When DDS = 0..................................................................................................... 199
Overview.............................................................................................................. 200
Basic Timing........................................................................................................ 200
Wait Control ........................................................................................................ 202
Operation ............................................................................................................. 203
Pin States in Idle Cycle ........................................................................................ 208
Features................................................................................................................ 217
Block Diagram ..................................................................................................... 218
Overview of Functions......................................................................................... 219
Pin Configuration................................................................................................. 221
Register Configuration......................................................................................... 222
Memory Address Registers (MAR) ..................................................................... 224
I/O Address Register (IOAR) .............................................................................. 225
Execute Transfer Count Register (ETCR) ........................................................... 225
Rev.6.00 Sep. 27, 2007 Page xv of xxx
REJ09B0220-0600