D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 569

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.2.3
NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output.
During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in
PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH
and NDRL addresses differ depending on whether pulse output groups have the same output
trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access.
NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are
not initialized in software standby mode.
11.2.4
The NDRH and NDRL addresses differ depending on whether pulse output groups have the same
output trigger or different output triggers.
Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the
same compare match event, the NDRH address is H'FF4C. The upper 4 bits belong to group 3 and
the lower 4 bits to group 2. Address H'FF4E consists entirely of reserved bits that cannot be
modified and are always read as 1.
Address H'FF4C
Address H'FF4E
If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address
is H'FF4D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FF4F
consists entirely of reserved bits that cannot be modified and are always read as 1.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Notes on NDR Access
Next Data Registers H and L (NDRH, NDRL)
:
:
:
:
NDR15
R/W
—
—
7
0
7
1
NDR14
R/W
—
—
6
0
6
1
NDR13
R/W
—
—
5
0
5
1
Section 11 Programmable Pulse Generator (PPG)
NDR12
R/W
—
—
4
0
4
1
Rev.6.00 Sep. 27, 2007 Page 537 of 1268
NDR11
R/W
—
—
3
0
3
1
NDR10
R/W
—
—
2
0
2
1
REJ09B0220-0600
NDR9
R/W
—
—
1
0
1
1
NDR8
R/W
—
—
0
0
0
1