D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 832

IC H8S/2300 MCU ROMLESS 128QFP

D12321VF25V

Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12321VF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
D12321VF25V
Manufacturer:
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Quantity:
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Part Number:
D12321VF25V
Manufacturer:
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Quantity:
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Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 ROM
19.13.9 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 19.27.
In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set
to 1 in SYSCR2 (except RAMER).
Table 19.27 Flash Memory Registers
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
System control register 2
RAM emulation register
Notes: 1. Lower 16 bits of the address.
Rev.6.00 Sep. 27, 2007 Page 800 of 1268
REJ09B0220-0600
2. Flash memory. Registers selection is performed by the FLSHE bit in system control
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
4. When a high level is input to the FWE pin, the initial value is H'80.
5. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
7. The SYSCR2 register can only be used in the F-ZTAT version. In the mask ROM
register 2 (SYSCR2).
writes are invalid. Writes are also disabled when the FWE bit is cleared to 0 in
FLMCR1.
FLMCR1 is not set, these registers are initialized to H'00.
for these registers, the access requiring 2 states.
version this register will return an undefined value if read, and cannot be modified.
Abbreviation R/W
FLMCR1 *
FLMCR2 *
EBR1 *
EBR2 *
SYSCR2 *
RAMER
6
6
6
6
7
R/W *
R/W *
R/W *
R/W *
R/W
R/W
3
3
3
3
H'00/H'80 *
H'00
H'00 *
H'00 *
H'00
H'00
Initial Value
5
5
4
H'FEDB
Address *
H'FFC8 *
H'FFC9 *
H'FFCA *
H'FFCB *
H'FF42
2
2
2
2
1

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