D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 420

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 I/O Ports
9.7
9.7.1
Port 6 is an 8-bit I/O port. Port 6 pins also function as interrupt input pins (IRQ
DMAC * I/O pins (DREQ
CS
pins P6
output can be performed by setting PFCR2. Pins P6
9.6 shows the port 6 pin configuration.
Note: * The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 388 of 1268
REJ09B0220-0600
Note: * The TEND
7
). The functions of pins P6
7
, P6
Port 6
Overview
6
, P6
Port 6
1
, and P6
1
, DREQ
0
0
, TEND
1
change according to the operating mode. Switching of CS
, TEND
Port 6 pins
P6
P6
P6
P6
P6
P6
P6
P6
7
6
5
4
3
2
1
0
5
/ IRQ
/ IRQ
/ IRQ
/ IRQ
/ TEND
/ DREQ
/ TEND
/ DREQ
to P6
Figure 9.6 Port 6 Pin Functions
0
, and DREQ
0
, DREQ
3
2
1
0
/ CS
/ CS
2
1
0
1
0
are the same in all operating modes, while the functions of
/ CS
/ CS
7
6
5
4
1
, and TEND
0
pin functions are not supported in the H8S/2321.
7
to P6
P6
P6
Pin functions in modes 4 to 6
P6
P6
P6
P6
P6
P6
P6
Pin functions in mode 7
P6
P6
P6
P6
P6
P6
P6
1
), and bus control output pins (CS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
4
(I/O) / IRQ
(I/O) / IRQ
(I/O) / IRQ
(I/O) / IRQ
(I/O) / TEND
(I/O) / DREQ
(I/O) / TEND
(I/O) / DREQ
(I/O) / IRQ
(I/O) / IRQ
(I/O) / IRQ
(I/O) / IRQ
(I/O) / TEND
(I/O) / DREQ
(I/O) / TEND
(I/O) / DREQ
are Schmitt-triggered inputs. Figure
3
2
1
0
3
2
1
0
(input) / CS
(input) / CS
(input)
(input)
(input)
(input)
(input)
(input)
1
0
1
0
1
0
1
0
* (output)
* (output) / CS
* (output)
* (output)
* (input)
* (input) / CS
* (input)
* (input)
7
6
0
(output)
(output)
to IRQ
4
5
(output)
(output)
4
to CS
3
),
4
7
to