D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 244

IC H8S/2300 MCU ROMLESS 128QFP

D12321VF25V

Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12321VF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller
6.10.4
Figure 6.37 shows the timing for transition to the bus released state.
Rev.6.00 Sep. 27, 2007 Page 212 of 1268
REJ09B0220-0600
Address bus
HWR, LWR
BREQO *
[1]
[2]
[3]
[4]
[5]
[6]
Note: * Output only when BREQOE is set to 1.
Data bus
BREQ
BACK
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
BREQO signal goes high 1.5 clocks after BACK signal goes high.
Transition Timing
RD
AS
φ
T
0
Figure 6.37 Bus Released State Transition Timing
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
[2]
2
state.
External bus released state
[3]
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
[5]
cycle
CPU
[6]

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