D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 178

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Bus Controller
6.1.3
Table 6.1 summarizes the pins of the bus controller.
Table 6.1
Name
Address strobe
Read
High write/write enable
Low write
Chip select 0
Chip select 1
Chip select 2/row address
strobe 2
Chip select 3/row address
strobe 3
Chip select 4/row address
strobe 4
Chip select 5/row address
strobe 5
Rev.6.00 Sep. 27, 2007 Page 146 of 1268
REJ09B0220-0600
Pin Configuration
Bus Controller Pins
Symbol
AS
RD
HWR
LWR
CS0
CS1
CS2
CS3
CS4
CS5
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Function
Strobe signal indicating that address output
on address bus is enabled.
Strobe signal indicating that external space
is being read.
Strobe signal indicating that external space
is to be written, and upper half (D
data bus is enabled.
2-CAS DRAM write enable signal * .
Strobe signal indicating that external space
is to be written, and lower half (D
data bus is enabled.
Strobe signal indicating that area 0 is
selected.
Strobe signal indicating that area 1 is
selected.
Strobe signal indicating that area 2 is
selected.
DRAM row address strobe signal when
area 2 is in DRAM space * .
Strobe signal indicating that area 3 is
selected.
DRAM row address strobe signal when
area 3 is in DRAM space * .
Strobe signal indicating that area 4 is
selected.
DRAM row address strobe signal when
area 4 is in DRAM space * .
Strobe signal indicating that area 5 is
selected.
DRAM row address strobe signal when
area 5 is in DRAM space * .
7
15
to D
to D
0
) of
8
) of