D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 256
![IC H8S/2300 MCU ROMLESS 128QFP](/photos/12/19/121977/d12321vf25v_sml.jpg)
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 DMA Controller (Not Supported in the H8S/2321)
7.2.1
MAR is a 32-bit readable/writable register that specifies the transfer source address or destination
address.
The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control
Register (DMACR).
MAR is not initialized by a reset or in standby mode.
Rev.6.00 Sep. 27, 2007 Page 224 of 1268
REJ09B0220-0600
Bit
MAR
Initial value :
R/W
Bit
MAR
Initial value :
R/W
Memory Address Registers (MAR)
:
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
:
:
:
31
15
—
—
0
*
30
14
—
—
0
*
29
13
—
—
0
*
28
12
—
—
0
*
27
11
—
—
0
*
26
10
—
—
0
*
25
—
—
0
9
*
24
— R/W R/W R/W R/W R/W R/W R/W R/W
—
0
8
*
23
7
*
*
22
6
*
*
21
*
5
*
20
4
*
*
19
3
*
*
18
2
*
*
*: Undefined
17
1
*
*
16
0
*
*
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