D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 430
![IC H8S/2300 MCU ROMLESS 128QFP](/photos/12/19/121977/d12321vf25v_sml.jpg)
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 I/O Ports
Port Function Control Register 1 (PFCR1)
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to
H'0F by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: Only 0 should be written to these bits.
Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A
in modes 4 to 6.
Bit 3
A23E
0
1
Bit 2—Address 22 Enable (A22E): Enables or disables address output 22 (A
in modes 4 to 6.
Bit 2
A22E
0
1
Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A
in modes 4 to 6.
Bit 1
A21E
0
1
Rev.6.00 Sep. 27, 2007 Page 398 of 1268
REJ09B0220-0600
Bit
Initial value :
R/W
:
:
Description
DR is output when PA7DDR = 1
A
Description
DR is output when PA6DDR = 1
A
Description
DR is output when PA5DDR = 1
A
23
22
21
is output when PA7DDR = 1
is output when PA6DDR = 1
is output when PA5DDR = 1
R/W
—
7
0
R/W
—
6
0
R/W
—
5
0
R/W
—
4
0
A23E
R/W
3
1
A22E
R/W
2
1
23
22
21
). This bit is valid
). This bit is valid
). This bit is valid
A21E
R/W
1
1
(Initial value)
(Initial value)
(Initial value)
A20E
R/W
0
1
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