D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 461
![IC H8S/2300 MCU ROMLESS 128QFP](/photos/12/19/121977/d12321vf25v_sml.jpg)
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
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Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
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9.13.2
Table 9.24 shows the port F register configuration.
Table 9.24 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Port function control register 2
System control register
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
Modes 4 to 6
Mode 7
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to
H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used
to select whether the bus control output pins retain their output state or become high-impedance
when a transition is made to software standby mode.
Bit
Initial value :
R/W
Initial value :
R/W
2. Initial value depends on the mode.
Register Configuration
:
:
:
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
W
W
7
1
0
W
W
6
0
0
SYSCR
Abbreviation
PFDDR
PFDR
PORTF
PFCR2
W
W
5
0
0
W
W
4
0
0
R/W
W
R/W
R/W
R/W
R
Rev.6.00 Sep. 27, 2007 Page 429 of 1268
W
W
3
0
0
Initial Value
H'80/H'00 *
H'00
Undefined
H'30
H'01
W
W
2
0
0
2
Section 9 I/O Ports
REJ09B0220-0600
W
W
1
0
0
Address *
H'FEBE
H'FF6E
H'FF5E
H'FFAC
H'FF39
W
W
0
0
0
1
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