D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 644
![IC H8S/2300 MCU ROMLESS 128QFP](/photos/12/19/121977/d12321vf25v_sml.jpg)
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
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Section 14 Serial Communication Interface (SCI)
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF
0
1
Notes: RDR and the RDRF flag are not affected and retain their previous values when an error is
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER
0
1
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is
Rev.6.00 Sep. 27, 2007 Page 612 of 1268
REJ09B0220-0600
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
* The DMAC is not supported in the H8S/2321.
2. The receive data prior to the overrun error is retained in RDR, and the data received
cleared to 0.
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Description
[Clearing conditions]
•
•
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Description
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1 *
When 0 is written to RDRF after reading RDRF = 1
When the DMAC * or DTC is activated by an RXI interrupt and reads data from
RDR
2
(Initial value) *
(Initial value)
1
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