D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 567

IC H8S/2300 MCU ROMLESS 128QFP

D12321VF25V

Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12321VF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
D12321VF25V
Manufacturer:
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Quantity:
135
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.2
11.2.1
NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a
bit-by-bit basis.
If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically
transferred to the corresponding PODR bit when the TPU compare match event specified by PCR
occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from
NDR to PODR and the output value does not change.
NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They
are not initialized in software standby mode.
NDERH Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or
disable pulse output on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8
0
1
NDERH
Bit
Initial value :
R/W
NDERL
Bit
Initial value :
R/W
Register Descriptions
Next Data Enable Registers H and L (NDERH, NDERL)
:
:
:
:
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
NDER7
R/W
R/W
7
0
7
0
Description
Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not
transferred to POD15 to POD8)
Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred
to POD15 to POD8)
NDER6
R/W
R/W
6
0
6
0
NDER5
R/W
R/W
5
0
5
0
Section 11 Programmable Pulse Generator (PPG)
NDER4
R/W
R/W
4
0
4
0
Rev.6.00 Sep. 27, 2007 Page 535 of 1268
NDER3
R/W
R/W
3
0
3
0
NDER2
R/W
R/W
2
0
2
0
NDER1
REJ09B0220-0600
R/W
R/W
1
0
1
0
(Initial value)
NDER8
NDER0
R/W
R/W
0
0
0
0

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