D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 175

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.1
The chip has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas. The bus specifications, such as bus width and number of access states, can be set
independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU, DMA controller (DMAC) * , and data transfer controller (DTC).
Note: * The DMAC is not supported in the H8S/2321.
6.1.1
The features of the bus controller are listed below.
• Manages external address space in area units
• Basic bus interface
• DRAM interface *
• Burst ROM interface
⎯ In advanced mode, manages the external space as 8 areas of 2 Mbytes
⎯ Bus specifications can be set independently for each area
⎯ DRAM * /burst ROM interfaces can be set
⎯ Chip select (CS0 to CS7) can be output for areas 0 to 7
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
⎯ DRAM interface can be set for areas 2 to 5 (in advanced mode)
⎯ Row address/column address multiplexed output (8/9/10 bits)
⎯ 2-CAS access method
⎯ Burst operation (fast page mode)
⎯ T
⎯ Choice of CAS-before-RAS refreshing or self-refreshing
⎯ Burst ROM interface can be set for area 0
⎯ Choice of 1- or 2-state burst access
P
Overview
Features
cycle insertion to secure RAS precharging time
Section 6 Bus Controller
Rev.6.00 Sep. 27, 2007 Page 143 of 1268
Section 6 Bus Controller
REJ09B0220-0600