D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 189

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.2.5
Note: * This bit is reserved in the H8S/2321.
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, DMAC single address transfer, enabling or disabling of the write data buffer
function, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
0
1
Bit
Initial value :
R/W
Bus Control Register L (BCRL)
Description
External bus release is disabled. BREQ, BACK, and BREQO pins can be used as I/O
ports
External bus release is enabled
Description
BREQO output disabled. BREQO pin can be used as I/O port
BREQO output enabled
:
:
BRLE
R/W
7
0
BREQOE
R/W
6
0
EAE
R/W
5
1
R/W
—
4
1
Rev.6.00 Sep. 27, 2007 Page 157 of 1268
DDS *
R/W
3
1
R/W
—
2
1
Section 6 Bus Controller
WDBE *
REJ09B0220-0600
R/W
1
0
(Initial value)
(Initial value)
WAITE
R/W
0
0