D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 423

IC H8S/2300 MCU ROMLESS 128QFP

D12321VF25V

Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12321VF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Port Function Control Register 2 (PFCR2)
PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to
H'30 by a reset, and in hardware standby mode.
Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. For details, see section 9.6,
Port 5.
Bit 6—BREQO Pin Select (BREQOPS): Selects the BREQO output pin. For details, see section
9.6, Port 5.
Bit 5—CS167 Enable (CS167E): Enables or disables CS
bits to 0 before changing the CS167E bit setting.
Bit 5
CS167E
0
1
Bit 4—CS25 Enable (CS25E): Enables or disables CS
DDR bits to 0 before changing the CS25E bit setting.
Bit 4
CS25E
0
1
Bit 3—As Output Disable (ASOD): Enables or disables AS output. For details, see section 9.13,
Port F.
Bits 2 to 0—Reserved: These bits are always read as 0.
Bit
Initial value :
R/W
:
:
Description
CS
CS
Description
CS
CS
WAITPS
1
1
2
2
, CS
, CS
, CS
, CS
R/W
7
0
6
6
3
3
, and CS
, and CS
, CS
, CS
BREQOPS
4
4
, and CS
, and CS
R/W
6
0
7
7
output disabled (can be used as I/O ports)
output enabled
CS167E
5
5
output disabled (can be used as I/O ports)
output enabled
R/W
5
1
CS25E
R/W
4
1
2
Rev.6.00 Sep. 27, 2007 Page 391 of 1268
, CS
1
, CS
ASOD
3
R/W
, CS
3
0
6
, and CS
4
, and CS
R
7
2
0
output. Clear the DDR
5
output. Clear the
Section 9 I/O Ports
REJ09B0220-0600
R
1
0
(Initial value)
(Initial value)
R
0
0

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