D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 786

IC H8S/2300 MCU ROMLESS 128QFP

D12321VF25V

Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12321VF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

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Section 19 ROM
19.5.3
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE
bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a
read will return H'00 and writes are invalid.
The flash memory block configuration is shown in table 19.7.
19.5.4
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE
bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0). Bits 7 and 6 are reserved: they are always
read as 0 and cannot be modified. When on-chip flash memory is disabled, a read will return H'00,
and writes are invalid.
The flash memory block configuration is shown in table 19.7.
Rev.6.00 Sep. 27, 2007 Page 754 of 1268
REJ09B0220-0600
Bit
EBR1
Initial value :
R/W
Bit
EBR2
Initial value :
R/W
Erase Block Register 1 (EBR1)
Erase Block Registers 2 (EBR2)
:
:
:
:
R/W
EB7
7
0
7
0
R/W
EB6
6
0
6
0
EB13
R/W
R/W
EB5
5
0
5
0
EB12
R/W
R/W
EB4
4
0
4
0
EB11
EB3
R/W
R/W
3
0
3
0
EB10
R/W
R/W
EB2
2
0
2
0
R/W
R/W
EB1
EB9
1
0
1
0
R/W
R/W
EB0
EB8
0
0
0
0

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