D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 392
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
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Part Number:
D12321VF25V
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- Current page: 392 of 1304
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Section 9 I/O Ports
Pin
P1
TIOCC
Rev.6.00 Sep. 27, 2007 Page 360 of 1268
REJ09B0220-0600
2
/PO
0
10
/TCLKA
/
Selection Method and Pin Functions
The pin function is switched as shown below according to the combination of
the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0
in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in
TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.
Notes: 1. TIOCC
TPU Channel
0 Setting
P12DDR
NDER10
Pin function
TPU Channel
0 Setting
MD3 to MD0
IOC3 to IOC0
CCLR2 to
CCLR0
Output
function
2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to
3. TIOCD
B'10xx.
TPSC0 = B'100.
TCLKA input when channels 1 and 5 are set to phase counting
mode.
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting
(2) applies.
B'0000
B'0100
B'1xxx
0
0
input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =
output is disabled.
(2)
—
—
B'0000
Table Below (1)
TIOCC
B'0001 to
B'0011
B'0101 to
B'0111
compare
Output
output
(1)
—
—
—
0
output
B'001x
B'xx00
TCLKA input *
(2)
—
—
output *
mode 1
B'0010
PWM
input
P1
(1)
—
—
0
2
2
Other than B'xx00
Table Below (2)
TIOCC
3
mode 2
output
output
Other
B'101
PWM
than
P1
(1)
1
0
0
input *
2
B'0011
x: Don’t care
1
output
B'101
PO
(2)
—
1
1
10
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