D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 494
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 10 16-Bit Timer Pulse Unit (TPU)
Channel
3
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4
Rev.6.00 Sep. 27, 2007 Page 462 of 1268
REJ09B0220-0600
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this
Bit 7
IOD3
0
1
count clock, this setting is invalid and input capture is not generated.
setting is invalid and input capture/output compare is not generated.
Bit 6
IOD2
0
1
0
1
Bit 5
IOD1
0
1
0
1
0
1
*
Bit 4
IOD0 Description
0
*
0
1
0
1
1
0
1
0
1
*
TGR3D
is output
compare
register*
TGR3D
is input
capture
register *
2
2
Output disabled
Capture input
source is channel
4/count clock
Output disabled
Initial output is 0
output
Initial output is 1
output
Capture input
source is
TIOCD3 pin
Input capture at TCNT4 count-
up/count-down *
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
(Initial value)
*: Don’t care
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