EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet
EFM32G200F16
Specifications of EFM32G200F16
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EFM32G200F16 Summary of contents
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Reference Manual EFM32G Microcontroller Family • 32-bit ARM Cortex-M3 processor running MHz • 128 KB Flash and 16 KB RAM memory • Energy efficient and fast autonomous peripherals • Ultra low power Energy Modes ...
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Energy Friendly Microcontrollers 1.1 EFM32G Typical Applications EFM32G is the superior choice for demanding 8-, 16-, and 32-bit low energy applications. Portable and battery operated systems benefit from the 8-bit power consumption and cost combined with a high- performance ...
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About This Document This document contains reference material for the EFM32G family Gecko series of Microcontrollers. All modules and peripherals in the Gecko series devices are described in general terms. Not all modules are present in all devices and ...
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... USn_TX (USART n TX pin) The location for the pin names given in the module documentation can be found in the device-specific datasheet. 2.2 Related Documentation Further documentation on the EFM32G family and the ARM Cortex-M3 can be found at the Energy Micro and ARM web pages: www.energymicro.com www.arm.com 2010-09-06 - d0001_Rev1 ...
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System Overview 3.1 Introduction The EFM32G MCU is the world’s most energy friendly microcontroller. With a unique combination of the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection ...
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Dead-Time Insertion on TIMER0 • 16-bit Low Energy Timer • 24-bit Real-Time Counter • 3× 8-bit Pulse Counter • Asynchronous pulse counting/quadrature decoding • Watchdog Timer with dedicated RC oscillator @ 50 nA • Ultra low power precision analog ...
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Figure 3.1. Diagram of EFM32G Gecko Core and Memory ARM Cortex -M3 processor ™ Flash Debug RAM Program Interface Memory Memory Serial Interfaces External USART UART Bus Interface Low External Energy Interrupts UART™ Note In the block ...
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Table 3.1. Energy Mode Description Energy Mode Name EM0 – Energy Mode (Run mode) EM1 – Energy Mode (Sleep Mode) EM2 – Energy Mode ...
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Table 3.2. EFM32G Microcontroller Family 200F16 200F32 200F64 210F128 128 230F32 230F64 230F128 128 ...
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System Processor Cor bit ALU Hardware divider Control Logic Instruction Interface NVIC Interface 4.1 Introduction The ARM Cortex-M3 32-bit RISC processor provides outstanding computational performance and exceptional system ...
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Unaligned data storage and access • Continuous storage of data requiring different byte lengths • Data access in a single core access cycle • Integrated power modes • Sleep Now mode for immediate transfer to low power state • ...
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Table 4.1. Interrupt Request Lines (IRQ) IRQ # 2010-09-06 - ...
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Memory and Bus System ARM Cor Con t r olle r 5.1 Introduction The EFM32G contains 4 main memory segments which can be accessed by the Cortex-M3 ...
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Figure 5.1. System Address Space The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32G. When running code located in SRAM starting at this address, the Cortex-M3 uses the System bus interface to fetch instructions. ...
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To ...
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Table 5.2. Memory System Low Energy Peripherals Low energy peripherals Address range 0x4008A400 – 0x400BFFFF 0x4008A000 – 0x4008A3FF 0x40088400 – 0x40089FFF 0x40088000 – 0x400883FF 0x40086C00 – 0x40087FFF 0x40086800 – 0x40086BFF 0x40086400 – 0x400867FF 0x40086000 – 0x400863FF 0x40084800 – 0x40085FFF 0x40084400 ...
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Table 5.3. Memory System Peripherals Peripherals Address range 0x40010C00 – 0x4007FFFF 0x40010800 – 0x40010BFF 0x40010400 – 0x400107FF 0x40010000 – 0x400103FF 0x4000E400 – 0x4000FFFF 0x4000E000 – 0x4000E3FF 0x4000CC00 – 0x4000DFFF 0x4000C800 – 0x4000CBFF 0x4000C400 – 0x4000C7FF 0x4000C000 – 0x4000C3FF 0x4000A400 – ...
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Access Performance The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth single AHB interface. The Bus Matrix accepts new transfers to be initiated by each master in each cycle ...
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Writing Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to maintain data consistency and predictable operation. Due to synchronization, the write operation requires 3 positive ...
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Figure 5.3. Read operation form Low Energy Peripherals Core Clock Dom ain Core Clock Register 0 Register Register n Read Synchronizer Read Data 5.3.2 FREEZE register In every Low Energy Peripheral there is a <module_name>_FREEZE register ...
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Device Information (DI) Page The DI page contains calibration values, a unique identification number and other useful data. See the table below for a complete overview. Table 5.4. Device Information Table DI Address Register 0x0FE08020 CMU_LFRCOCTRL 0x0FE08028 CMU_HFRCOCTRL 0x0FE08030 ...
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DI Address Register 0x0FE081E0 HFRCO_CALIB_BAND_21 0x0FE081E1 HFRCO_CALIB_BAND_28 0x0FE081E2 RESERVED 0x0FE081E4 RESERVED 0x0FE081F0 UNIQUE_0 0x0FE081F4 UNIQUE_1 0x0FE081F8 MEM_INFO_FLASH 0x0FE081FA MEM_INFO_RAM 0x0FE081FC PART_NUMBER 0x0FE081FE PART_FAMILY 0x0FE081FF PROD_REV 2010-09-06 - d0001_Rev1.00 ...the world's most energy friendly microcontrollers Description [7:0]: 21 MHz tuning [7:0]: ...
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DBG - Debug Interface ARM Cor DBG 6.1 Introduction The EFM32G devices include hardware debug support through a 2-pin serial-wire debug interface. In addition there is also a 1-wire ...
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When debug access is locked, the debug interface remains accessible, but the connection to the Cortex- M3 core is blocked. This mechanism is controlled by the Authentication Access Port (AAP) as illustrated by Figure 6.1 (p. 24) . Figure 6.1. ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 AAP_CMD 0x004 AAP_CMDKEY 0x008 AAP_STATUS 0x0FC AAP_IDR 6.6 Register Description 6.6.1 AAP_CMD - Command Register Offset 0x000 Reset Access Name Bit Name Reset ...
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Bit Name Reset The key value must be written to this register to write enable the AAP_CMD register. Value Mode 0xCFACC118 WRITEEN 6.6.3 AAP_STATUS - Status Register Offset 0x008 Reset Access Name Bit Name Reset 31:1 Reserved To ensure compatibility ...
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MSC - Memory System Controller 01000101011011100110010101110010 01100111011110010010000001001101 01101001011000110111001001101111 00100000011100100111010101101100 01100101011100110010000001110100 01101000011001010010000001110111 01101111011100100110110001100100 00100000011011110110011000100000 01101100011011110111011100101101 01100101011011100110010101110010 01100111011110010010000001101101 01101001011000110111001001101111 01100011011011110110111001110100 01110010011011110110110001101100 01100101011100100010000001100100 01100101011100110110100101100111 01101110001000010100010101101110 7.1 Introduction The Memory System Controller (MSC) is the program memory unit ...
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Conditional branch target prefetch suppression • Cortex-M3 disfolding of if-then (IT) blocks • DMA read support in EM0 and EM1 • Command and status interface • Flash write and erase • Accessible from Cortex-M3 in EM0 • DMA write ...
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User Data (UD) Page Description This is the user data page in the information block. The page can be erased and written by software. The page is erased by the ERASEPAGE command of the MSC_WRITECMD register. Note that the ...
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The Revision number interpreted according to Table 7.3 (p. 30) . Table 7.3. Revision Number Interpretation Revision[7:0] 0x00 0x01 7.3.5 Post-reset Behavior Calibration values are automatically written to registers by the MSC before application code startup. The ...
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The instructions in the block then appear to execute in zero cycles. With this scheme, performance is optimized at the cost of higher energy consumption as the processor fetches more instructions from memory than it actually executes. To disable ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 MSC_CTRL 0x004 MSC_READCTRL 0x008 MSC_WRITECTRL 0x00C MSC_WRITECMD 0x010 MSC_ADDRB 0x018 MSC_WDATA 0x01C MSC_STATUS 0x02C MSC_IF 0x030 MSC_IFS 0x034 MSC_IFC 0x038 MSC_IEN 0x03C MSC_LOCK ...
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Bit Name Reset 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 2:0 MODE 0x1 After reset, the core clock is 14 MHz from the HFRCO and the MODE ...
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Bit Name Reset 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( WRITETRIG 0 Start write of the first word written to MSC_WDATA, then add 4 to ADDR ...
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Bit Name Reset 31:0 WDATA 0x00000000 The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of MSC_STATUS is set, otherwise the data is ignored. 7.5.7 MSC_STATUS - Status Register Offset ...
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Bit Name Reset 1 WRITE 0 Set when a write is done 0 ERASE 0 Set when erase is done 7.5.9 MSC_IFS - Interrupt Flag Set Register Offset 0x030 Reset Access Name Bit Name Reset 31:2 Reserved To ensure compatibility ...
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MSC_IEN - Interrupt Enable Register Offset 0x038 Reset Access Name Bit Name Reset 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( WRITE 0 Enable the write ...
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DMA - DMA Controller DMA controller 8.1 Introduction The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing the energy consumption and the workload of ...
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Scatter-gather (using the primary descriptor to configure the alternate descriptor) • Each channel has a programmable transfer length • A DMA channel can be triggered by any of several sources: • Communication modules (USART, UART, LEUART) • Timers (TIMER) ...
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It can also be used to reduce the system energy consumption by making the DMA work autonomously ...
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R_power Arbitrate after x DMA transfers b0001 b0010 b0011 b0100 b0101 b0110 b0111 x = 128 b1000 x = 256 b1001 x ...
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Channel Priority level Descending order of number setting channel priority 1 Default - 2 Default - 3 Default - 4 Default - 5 Default - 6 Default - 7 Default Lowest-priority DMA channel After a DMA transfer completes, the controller ...
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Description b010 Auto-request b011 Ping-pong b100 Memory scatter-gather using the primary data structure b101 Memory scatter-gather using the alternate data structure b110 Peripheral scatter-gather using the primary data structure b111 Peripheral scatter-gather using the alternate data structure Note The ...
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Figure 8.3 (p. 44) shows an example of a ping-pong DMA transaction. Figure 8.3. Ping-pong example R Task A: Prim ...
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Task B 7. The controller performs four DMA transfers. 8. The controller arbitrates. After the controller receives a request for this channel, the flow continues if the channel has the highest priority. 9. The controller performs four DMA transfers. 10. ...
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After this cycle completes, the controller performs another four DMA transfers using the primary data structure. The controller continues to switch from primary to alternate to primary… until either: • the host processor configures the alternate data ...
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Figure 8.4. Memory scatter-gather example Initialization: 1. Configure prim ary to enable the copy and D operations: cycle_ctrl = b100 Write the prim ary source data ory, using the structure shown in ...
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The controller generates an auto-request for the channel and then arbitrates. Task C 9. The controller performs task C. After it completes the task, it generates an auto-request for the channel and then arbitrates. Primary, copy D 10. T ...
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Bit Field Value Description 1 [13:4] n_minus_1 N Configures the controller to perform N DMA transfers, where multiple of four [3] next_useburst - When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after ...
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Primary, copy A 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A. Task A 2. The controller performs task A. 3. After the controller completes the task it ...
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Figure 8.6 (p. 51) ...
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Figure 8.7. Detailed memory map for the 8 channels, including the alternate data structure Unused Control Alternate for channel 7 Destination End Pointer Source End Pointer Unused Control Alternate for channel 1 Destination End Pointer Source End Pointer Unused Control ...
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Destination data end pointer The dst_data_end_ptr memory location contains a pointer to the end address of the destination data. Table 8.8 (p. 53) lists the bit assignments for this memory location. Table 8.8. dst_data_end_ptr bit assignments Bit Name Description ...
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Bit Name Description Note You must set dst_size to contain the same value that src_size contains. [27:26] src_inc Set the bits to control the source address increment. The address increment depends on the source data width as follows: Source data ...
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Bit Name Description [13:4] n_minus_1 Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require. ...
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Bit Name Description When the controller operates in peripheral scatter-gather mode, you must only use this value in the alternate data structure. At the start of a DMA cycle memory. After it performs ...
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Table 8.11. DMA cycle of 12 bytes using a halfword increment Initial values of channel_cfg, prior to the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11 End Pointer 0x5E7 0x5E7 0x5E7 ...
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Example 8.1. DMA Transfer 1. Configure the channel select for using USART1 with DMA channel 0 a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0 2. Configure the primary channel descriptor for DMA channel 0 a. Write XX (read address of USART1) ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 DMA_STATUS 0x004 DMA_CONFIG 0x008 DMA_CTRLBASE 0x00C DMA_ALTCTRLBASE 0x010 DMA_WAITSTATUS 0x014 DMA_CHSWREQ 0x018 DMA_CHUSEBURSTS 0x01C DMA_CHUSEBURSTC 0x020 DMA_CHREQMASKS 0x024 DMA_CHREQMASKC 0x028 DMA_CHENS 0x02C DMA_CHENC ...
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Register Description 8.7.1 DMA_STATUS - DMA Status Registers Offset 0x000 Reset Access Name Bit Name Reset 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 CHNUM 0x07 ...
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Bit Name Reset Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access is privileged. When CHPROT = 0 then HPROT is LOW and the access is ...
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DMA_WAITSTATUS - Channel Wait on Request Status Register Offset 0x010 Reset Access Name Bit Name Reset 31:0 WAITSTATUS 0x000000FF Status for wait on request for each channel. 8.7.6 DMA_CHSWREQ - Channel Software Request Register Offset 0x014 Reset Access Name ...
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DMA_CHUSEBURSTS - Channel Useburst Set Register Offset 0x018 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7USEBURSTS 0 See description ...
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Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7USEBURSTC 0 Write disable useburst setting for this channel. 6 CH6USEBURSTC 0 Write ...
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Bit Name Reset Write disable peripheral requests for this channel. 0 CH0REQMASKS 0 Write disable peripheral requests for this channel. 8.7.10 DMA_CHREQMASKC - Channel Request Mask Clear Register Offset 0x024 Reset Access Name Bit ...
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Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7ENS 0 Write enable this channel. Reading returns the enable status of the ...
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Bit Name Reset Write disable this channel. Note that the controller disables a channel, by setting the appropriate bit, when either it completes the DMA cycle reads a channel_cfg memory location which has cycle_ctrl = ...
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Bit Name Reset 7 CH7ALTC 0 Write select the primary structure for this channel. 6 CH6ALTC 0 Write select the primary structure for this channel. 5 CH5ALTC 0 Write select the ...
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DMA_CHPRIC - Channel Priority Clear Register Offset 0x03C Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7PRIC 0 Write to ...
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DMA_IF - Interrupt Flag Register Offset 0x1000 Reset Access Name Bit Name Reset 31 ERR 0 This flag is set when an error has occurred on the AHB bus. 30:8 Reserved To ensure compatibility with future devices, always write ...
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Bit Name Reset 6 CH6DONE 0 Write set the corresponding DMA channel complete interrupt flag. 5 CH5DONE 0 Write set the corresponding DMA channel complete interrupt flag. 4 CH4DONE 0 Write ...
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DMA_IEN - Interrupt Enable register Offset 0x100C Reset Access Name Bit Name Reset 31 ERR 0 Set this bit to enable interrupt on AHB bus error. 30:8 Reserved To ensure compatibility with future devices, always write bits to 0. ...
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Bit Name Reset Value Mode 0b000000 NONE 0b001000 ADC0 0b001010 DAC0 0b001100 USART0 0b001101 USART1 0b001110 USART2 0b010000 LEUART0 0b010001 LEUART1 0b010100 I2C0 0b011000 TIMER0 0b011001 TIMER1 0b011010 TIMER2 0b101100 UART0 0b110000 MSC 0b110001 AES 15:4 Reserved To ensure compatibility ...
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Bit Name Reset Value SOURCESEL = 0b011000 (TIMER0) 0b0000 0b0001 0b0010 0b0011 SOURCESEL = 0b011001 (TIMER1) 0b0000 0b0001 0b0010 0b0011 SOURCESEL = 0b011010 (TIMER2) 0b0000 0b0001 0b0010 0b0011 SOURCESEL = 0b101100 (UART0) 0b0000 0b0001 0b0010 SOURCESEL = 0b110000 (MSC) 0b0000 ...
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RMU - Reset Management Unit RESETn POWERON BROWNOUT LOCKUP SYSRESETREQ WATCHDOG 9.1 Introduction The RMU is responsible for handling the reset functionality of the EFM32G. 9.2 Features • Reset sources • Power-on Reset (POR) ...
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Figure 9.1. RMU Reset Input Sources and Connections. Reset Managem ent Unit POR BROWNOUT_UNREGn V DD BOD V BROWNOUT_REGn DD_REGULATED BOD RESETn Filter RCCLR RMU_RSTCAUSE WDOG LOCKUP LOCKUPRDIS SYSREQRST 9.3.1 RMU_RSTCAUSE Register The RMU_RSTCAUSE register indicates the reason for the ...
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EFM32G is kept in reset state. The operation of the POR is illustrated in Figure 9.2 (p. 77) , with the active low POWERONn reset signal. The reason for the “unknown” region is that the ...
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A Cortex-M3 lockup gives immediate indication of seriously errant kernel software. This is the result of the core being locked up due to an unrecoverable exception following the activation of the processor’s built in system state protection hardware. For more ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 RMU_CTRL 0x004 RMU_RSTCAUSE 0x008 RMU_CMD 9.5 Register Description 9.5.1 RMU_CTRL - Control Register Offset 0x000 Reset Access Name Bit Name Reset 31:1 Reserved ...
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Bit Name Reset 3 EXTRST 0 Set if an external pin reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 76) for details on how to interpret this bit. 2 BODREGRST 0 Set if a ...
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EMU - Energy Management Unit 10.1 Introduction The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32G microcontrollers. Each energy mode manages if the CPU and the various peripherals are ...
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Functional Description The Energy Management Unit (EMU) is responsible for managing the wide range of energy modes available in EFM32G. An overview of the EMU module is shown in Figure 10.1 (p. 82) . Figure 10.1. EMU Overview Peripheral ...
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Figure 10.2. EMU Energy Mode Transitions Act ive m ode Low energy m odes No direct transitions between EM1, EM2 or EM3 are available, as can also be seen from Figure 10.2 (p. 83) . Instead, a wakeup will transition ...
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Table 10.1. EMU Energy Mode Overview Wakeup time to EM0 MCU clock tree High frequency peripheral clock trees Core voltage regulator High frequency oscillator full functionality Low frequency peripheral clock trees Low frequency oscillator Real Time Counter ...
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The low frequency oscillator and clock trees are active • Low frequency peripheral functionality (RTC, Watchdog, LCD, LEUART, I available • Wakeup through peripheral interrupt or asynchronous pin interrupt • RAM and register values are preserved 10.3.1.4 EM3 • ...
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Table 10.3. EMU Wakeup Triggers from Low Energy Modes Peripheral Wakeup Trigger RTC Any enabled interrupt LEUART Receive / transmit Any enabled interrupt Receive address recognition LETIMER Any enabled interrupt PCNT Any enabled interrupt ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 EMU_CTRL 0x004 EMU_MEMCTRL 0x008 EMU_LOCK 0x024 EMU_AUXCTRL 10.5 Register Description 10.5.1 EMU_CTRL - Control Register Offset 0x000 Reset Access Name Bit Name Reset ...
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Bit Name Reset 2:0 POWERDOWN 0x0 Individual 4KB RAM block power-down. When a block is powered down, it cannot be powered up again. The block will be powered up after the reset. Block 0 (address range 0x20000000-0x20000FFF) may never be ...
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Bit Name Reset Write to 1 and then 0 to clear the POR, BOD and WDOG reset cause register bits. See also the Reset Management Unit (RMU). 2010-09-06 - d0001_Rev1.00 ...the world's most energy friendly microcontrollers Access Description 89 www.energymicro.com ...
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CMU - Clock Management Unit WDOG clock LETIMER clock LCD clock Oscillators CMU Peripheral A clock Peripheral B clock Peripheral C clock Peripheral C clock CPU clock 11.1 Introduction The Clock Management Unit (CMU) ...
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Selectable clocks can be output on two pins for use externally. • Auxiliary 14 MHz RC oscillator (AUXHFRCO) for flash programming and debug trace. 11.3 Functional Description An overview of the CMU is shown in Figure 11.1 (p. 92) ...
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Figure 11.1. CMU Overview AUXCLK AUXHFRCO Tim eout (Flash Program m ing) CMU_HFPERCLKDIV.HFPERCLKEN HFXO Tim eout Tim eout HFRCO CMU_CMD.HFCLKSEL LFXO Tim eout LFRCO Tim eout CMU_LFCLKSEL.LFA CMU_LFCLKSEL.LFB ULFRCO WDOG_CTRL.CLKSEL 2010-09-06 - d0001_Rev1.00 ...the world's most energy friendly microcontrollers Debug ...
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System Clocks 11.3.1.1 HFCLK - High Frequency Clock HFCLK is the selected High Frequency Clock. This clock is used by the CMU and drives the two prescalers that generate HFCORECLK and HFPERCLK. The HFCLK can be driven by a ...
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LFBCLK - Low Frequency B Clock LFBCLK is the selected clock for the Low Energy B Peripherals. There are three selectable sources for LFBCLK: LFRCO, LFXO and HFCORECLK reset, the LFBCLK source is set to LFRCO. However, note that ...
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Software can switch between the different clock sources at run-time. E.g., when the HFRCO is the clock source, software can switch to HFXO by writing the field HFCLKSEL in the CMU_CMD command register. See Figure 11.2 (p. 95) for a ...
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Figure 11.3. CMU Switching from HFRCO to HFXO after HFXO is ready CMU_CMD.HFCLKSEL CMU_OSCENCMD.HFRCOEN CMU_OSCENCMD.HFRCODIS CMU_OSCENCMD.HFXOEN CMU_OSCENCMD.HFXODIS CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_STATUS.HFRCOSEL CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_STATUS.HFXOSEL HFCLK HFRCO HFXO Switching clock source for LFACLK and LFBCLK is done by setting the LFA and ...
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Figure 11.5. LFXO Pin Connection It is possible to connect an external clock source to HFXTAL_N/LFXTAL_N pin of the HFXO or LFXO oscillator. By configuring the HFXOMODE/LFXOMODE fields in CMU_CTRL, the HFXO/LFXO can be bypassed. 11.3.3.2 HFRCO, LFRCO and AUXHFRCO ...
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Output Clock on a Pin It is possible to configure the CMU to output clocks on two pins. This clock selection is done using CLKOUTSEL0 and CLKOUTSEL1 fields in CMU_CTRL. The output pins must be configured in the CMU_ROUTE ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 CMU_CTRL 0x004 CMU_HFCORECLKDIV 0x008 CMU_HFPERCLKDIV 0x00C CMU_HFRCOCTRL 0x010 CMU_LFRCOCTRL 0x014 CMU_AUXHFRCOCTRL 0x018 CMU_CALCTRL 0x01C CMU_CALCNT 0x020 CMU_OSCENCMD 0x024 CMU_CMD 0x028 CMU_LFCLKSEL 0x02C CMU_STATUS ...
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Register Description 11.5.1 CMU_CTRL - CMU Control Register Offset 0x000 Reset Access Name Bit Name Reset 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CLKOUTSEL1 0 ...
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Bit Name Reset Value Mode 0 XTAL 1 BUFEXTCLK 2 DIGEXTCLK 10:9 HFXOTIMEOUT 0x3 Configures the start-up delay for HFXO. Value Mode 0 8CYCLES 1 256CYCLES 2 1KCYCLES 3 16KCYCLES 8 Reserved To ensure compatibility with future devices, always write ...
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Bit Name Reset 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3:0 HFCORECLKDIV 0x0 Specifies the clock divider for HFCORECLK. Value Mode 0 HFCLK 1 HFCLK2 2 HFCLK4 ...
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CMU_HFRCOCTRL - HFRCO Control Register Offset 0x00C Reset Access Name Bit Name Reset 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 16:12 SUDELAY 0x00 Always write this ...
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CMU_AUXHFRCOCTRL - AUXHFRCO Control Register Offset 0x014 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:0 TUNING 0x80 This value has ...
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CMU_CALCNT - Calibration Counter Register Offset 0x01C Reset Access Name Bit Name Reset 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:0 CALCNT 0x00000 Write top value ...
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Bit Name Reset 2 HFXOEN 0 Enables the HFXO. 1 HFRCODIS 0 Disables the HFRCO. HFRCOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRCO if this oscillator is selected as the source for HFCLK. 0 HFRCOEN ...
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Bit Name Reset Value Mode 1 LFRCO 2 LFXO 3 HFCORECLKLEDIV2 1:0 LFA 0x1 Selects the clock source for LFACLK. Value Mode 0 DISABLED 1 LFRCO 2 LFXO 3 HFCORECLKLEDIV2 11.5.12 CMU_STATUS - Status Register Offset 0x02C Reset Access Name ...
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Bit Name Reset 3 HFXORDY 0 HFXO is enabled and start-up time has exceeded. 2 HFXOENS 0 HFXO is enabled. 1 HFRCORDY 1 HFRCO is enabled and start-up time has exceeded. 0 HFRCOENS 1 HFRCO is enabled. 11.5.13 CMU_IF - ...
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Bit Name Reset 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CALRDY 0 Write set the Calibration Ready(completed) Interrupt Flag 4 AUXHFRCORDY 0 Write ...
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CMU_IEN - Interrupt Enable Register Offset 0x03C Reset Access Name Bit Name Reset 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CALRDY 0 Set to enable ...
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CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 Offset 0x044 Reset Access Name Bit Name Reset 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( I2C0 ...
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CMU_SYNCBUSY - Synchronization Busy Register Offset 0x050 Reset Access Name Bit Name Reset 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( LFBPRESC0 0 Used to check ...
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Bit Name Reset 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( REGFREEZE 0 When set, the update of the Low Frequency clock control registers is postponed until ...
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CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg) Offset 0x068 Reset Access Name Bit Name Reset 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9:8 ...
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Bit Name Reset Value Mode 10 DIV1024 11 DIV2048 12 DIV4096 13 DIV8192 14 DIV16384 15 DIV32768 11.5.24 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) Offset 0x070 Reset Access Name Bit Name Reset 31:6 Reserved To ensure ...
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Bit Name Reset 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( PCNT2CLKSEL 0 This bit controls which clock that is used for the PCNT. Value Mode 0 ...
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Bit Name Reset Value Mode 2 DIV4 3 DIV8 4 DIV16 5 DIV32 6 DIV64 7 DIV128 3 VBOOSTEN 0 This bit enables/disables the VBOOST function. 2:0 FDIV 0x0 These bits controls the framerate according to this formula: LFACLK the ...
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Bit Name Reset 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000 Write any other value CMU_HFPERCLKDIV, CMU_HFRCOCTRL, CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_OSCENCMD, CMU_CMD, CMU_LFCLKSEL, CMU_HFCORECLKEN0, CMU_HFPERCLKEN0, CMU_LFACLKEN0, ...
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WDOG - Watchdog Timer Counter value Watchdog clear Tim eout period 12.1 Introduction The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. ...
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Clock Source Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL. The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be written to prevent accidental disabling ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 WDOG_CTRL 0x004 WDOG_CMD 0x008 WDOG_SYNCBUSY 12.5 Register Description 12.5.1 WDOG_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see ...
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Bit Name Reset 7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( SWOSCBLOCK 0 Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 ...
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Bit Name Reset 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CLEAR 0 Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout. ...
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PRS - Peripheral Reflex System Tim er ADC DMA 13.1 Introduction The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each other without involving the ...
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Channel Functions Different functions can be applied to a reflex signal within the PRS. Each channel includes an edge detector to enable generation of pulse signals from level signals also possible to generate output Reflex signals by ...
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Module RTC TIMER UART USART VCMP 13.3.3 Consumers Consumer peripherals (Listed in Table 13.2 (p. 126) ) can be set to listen to a PRS channel and perform an action based on the signal received on that channel. Most consumers ...
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Module UART USART 13.3.4 Example The example below (illustrated in Figure 13.2 (p. 127) ) shows how to set up ADC0 to start single conversions every time TIMER0 overflows (one HFPERCLK cycle high pulse), using PRS channel 5: • Set ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 PRS_SWPULSE 0x004 PRS_SWLEVEL 0x010 PRS_CH0_CTRL 0x014 PRS_CH1_CTRL 0x018 PRS_CH2_CTRL 0x01C PRS_CH3_CTRL 0x020 PRS_CH4_CTRL 0x024 PRS_CH5_CTRL 0x028 PRS_CH6_CTRL 0x02C PRS_CH7_CTRL 13.5 Register Description 13.5.1 ...
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PRS_SWLEVEL - Software Level Register Offset 0x004 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7LEVEL 0 See bit 0. ...
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Bit Name Reset Value Mode 1 POSEDGE 2 NEGEDGE 3 BOTHEDGES 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 21:16 SOURCESEL 0x00 Select input source to PRS channel. ...
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Bit Name Reset Value 0b001 0b010 SOURCESEL = 0b011100 (TIMER0) 0b000 0b001 0b010 0b011 0b100 SOURCESEL = 0b011101 (TIMER1) 0b000 0b001 0b010 0b011 0b100 SOURCESEL = 0b011110 (TIMER2) 0b000 0b001 0b010 0b011 0b100 SOURCESEL = 0b101000 (RTC) 0b000 0b001 0b010 ...
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EBI - External Bus Interface EBI Parallel Interface (EFM32) 14.1 Introduction The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The interface is memory mapped ...
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EBI_AD bus. When a write operation is requested, the address and subsequently the write data are transferred onto the EBI_AD bus as the EBI_WEn pin is activated. The detailed operation in the supported modes is presented ...
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Address Mode In this mode, 16-bit address and 16-bit data is supported, which requires the utilization of a latch. An illustration of such a setup is shown in Figure 14.4 (p. 134) Note In this mode the 16-bit ...
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Address Mode This mode allows 24-bit address with 8-bit data. The upper 8 bits of the EBI_AD lines are used for the highest 16-bits of the address while the lower 8 bits is used for the lowest address ...
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Table 14.1. EBI Timing Reference Parameter t Address Setup ALS before ALE high t Address Hold after ALH ALE high t ALE Width ALW t Address Setup ARS before RE high t Address Hold after ARH RE high t Data ...
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ARDYEN bit in the EBI_CTRL register also possible to enable a timeout check, which generates a bus error if the ARDY is not deasserted within the timeout period. This prevents system stalemate ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 EBI_CTRL 0x004 EBI_ADDRTIMING 0x008 EBI_RDTIMING 0x00C EBI_WRTIMING 0x010 EBI_POLARITY 0x014 EBI_ROUTE 14.5 Register Description 14.5.1 EBI_CTRL - Control Register Offset 0x000 Reset Access ...
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EBI_ADDRTIMING - Address Timing Register Offset 0x004 Reset Access Name Bit Name Reset 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 9:8 ADDRHOLD 0x1 Sets the number ...
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EBI_WRTIMING - Write Timing Register Offset 0x00C Reset Access Name Bit Name Reset 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 17:16 WRHOLD 0x1 Sets the number ...
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Bit Name Reset Value Mode 0 ACTIVELOW 1 ACTIVEHIGH 1 REPOL 0 Sets the polarity of the EBI_REn line. Value Mode 0 ACTIVELOW 1 ACTIVEHIGH 0 CSPOL 0 Sets the polarity of the EBI_CSn line. Value Mode 0 ACTIVELOW 1 ...
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Inter-Integrated Circuit Interface Other I C Other I m aster slave 15.1 Introduction 2 The I C module provides an interface between the MCU and a serial ...
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Functional Description 2 An overview of the I C module is shown in Figure 15.1 (p. 143 Figure 15. Overview I2Cn_SDA Pin ctrl I2Cn_SCL 2 15.3.1 I C-Bus Overview 2 The I C-bus uses two ...
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The GPIO drive strength can be used to control slew rate. 15.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I the bus begin with a START condition (S) and end ...
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Examples transfers are shown in Figure 15.5 (p. 145) , Figure 15.6 (p. 145) , and Figure 15.7 (p. 145) . The identifiers used are: • ADDR - Address • DATA - Data • ...
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When performing a master transmitter operation, the master transmits the two address bytes and then the remaining data, as shown in Figure 15.8 (p. 146 Figure 15. Master Transmitter/Slave Receiver with 10-bit Address S ADDR (1st ...
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I2Cn_CTRL must be reset. This should be done regardless whether the slave is going to be re-enabled or not. 15.3.4 Clock Generation The SCL clock signal generated by the I The clock is generated as a division of the peripheral ...
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Buffers 15.3.6.1 Transmit Buffer and Shift Register 2 The I C transmitter is double buffered through the transmit buffer and transmit shift register as shown in Figure 15.1 (p. 143 byte is loaded into the transmit buffer ...
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After the address has been transmitted, a sequence of bytes can be read from or written to the slave, depending on the value of the R/W bit (bit 0 in the address byte). If the bit was cleared, the master ...
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Interactions 2 Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends ...
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STATUS register. A pending START command can for instance be identified by PSTART having a high value. 2 Whenever the I C module requires an interaction, it checks the ...
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I2Cn_STATE will then be 0x57. As seen in the table, the I the address is not available after a repeated start condition. To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 ...
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I2Cn_STATE Description - Data transmitted 0xD7 Data transmitted,ACK received 0xDF Data transmitted,NACK received - Stop transmitted - Arbitration lost 15.3.7.5 Master Receiver To receive data from a slave, the master must operate as a master receiver, see Table 15.5 (p. ...
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As when operating as a master transmitter, arbitration can be lost as a master receiver. When this happens the ARBLOST interrupt flag in I2Cn_IF is set, and the master has a possibility of being selected as a slave given the ...
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I2Cn_STATE Description - Arbitration lost 15.3.8 Bus States The I2Cn_STATE register can be used to determine which state the given time. The register consists of the STATE bit-field, which shows which state the any ...
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Slave State Machine The slave state machine is shown in Figure 15.11 (p. 156) . The dotted lines show where I interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let ...
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After a START or repeated START condition, the bus master will transmit an address along with bit. If there is no room in the receive shift register for the address, the bus will be held by the ...
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Table 15. Slave Transmitter I2Cn_STATE Description 0x41 Repeated START received 0x73 ADDR + R received - Data transmitted 0xD5 Data transmitted, ACK received 0xDD Data transmitted, NACK received - Stop received - Arbitration lost 15.3.9.4 Slave Receiver ...
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See Table 15.9 (p. 159) for more information. 2 Table 15. Slave Receiver I2Cn_STATE Description - Repeated START received 0x71 ADDR + W received 0xB1 Data received - Stop received - Arbitration lost 15.3.10 Transfer Automation 2 ...
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Using 10-bit Addresses When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX are the two most significant bits of the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address matches will now be ...
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Many slave-only devices operating case that SCL is stuck LOW, the advice is to apply a hardware reset signal to the slaves on the bus. If this does not work, cycle the power to the devices in ...
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Transmit buffer and shift register empty. No data to send • Transmit buffer empty 15.3.14 Interrupts The interrupts generated by the I interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 I2Cn_CTRL 0x004 I2Cn_CMD 0x008 I2Cn_STATE 0x00C I2Cn_STATUS 0x010 I2Cn_CLKDIV 0x014 I2Cn_SADDR 0x018 I2Cn_SADDRMASK 0x01C I2Cn_RXDATA 0x020 I2Cn_RXDATAP 0x024 I2Cn_TXDATA 0x028 I2Cn_IF 0x02C I2Cn_IFS ...
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Bit Name Reset When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated. Value Description 0 A bus idle timeout has no effect on the bus state bus idle timeout ...
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Bit Name Reset Value Description 0 Software must give one ACK command for each ACK transmitted on the I 1 Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 SLAVE 0 Set this bit to allow ...
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I2Cn_STATE - State Register Offset 0x008 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:5 STATE 0x0 The state of any ...
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Bit Name Reset 8 RXDATAV 0 Set when data is available in the receive buffer. Cleared when the receive buffer is empty. 7 TXBL 1 Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and ...
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Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:1 ADDR 0x00 Specifies the slave address of the device. 0 Reserved To ensure compatibility with future ...
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I2Cn_RXDATAP - Receive Buffer Data Peek Register Offset 0x020 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:0 RXDATAP 0x00 Use ...
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Bit Name Reset Set on each clock low timeout. The timeout value can be set in CLTO bitfield in the I2Cn_CTRL register. 14 BITO 0 Set on each bus idle timeout. The timeout value can be set in the BITO ...
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Bit Name Reset 16 SSTOP 0 Write set the SSTOP interrupt flag. 15 CLTO 0 Write set the CLTO interrupt flag. 14 BITO 0 Write set the BITO interrupt flag. 13 ...
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Bit Name Reset Write clear the SSTOP interrupt flag. 15 CLTO 0 Write clear the CLTO interrupt flag. 14 BITO 0 Write clear the BITO interrupt flag. 13 RXUF 0 Write ...
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Bit Name Reset 15 CLTO 0 Enable interrupt on clock low timeout. 14 BITO 0 Enable interrupt on bus idle timeout. 13 RXUF 0 Enable interrupt on receive buffer underflow. 12 TXOF 0 Enable interrupt on transmit buffer overflow. 11 ...
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Bit Name Reset 9:8 LOCATION 0x0 2 Decides the location of the I C I/O pins. Value Mode 0 LOC0 1 LOC1 2 LOC2 3 LOC3 7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More ...
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USART - Universal Synchronous Asynchronous Receiver/Transmitter DMA RAM controller USART RX/ MISO TX/ MOSI CLK CS EFM32 16.1 Introduction The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART very flexible serial I/O ...
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Configurable number of data bits, 4-16 (plus the parity bit, if enabled) • HW parity bit generation and check • Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2 • HW collision detection • Multi-processor mode ...
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Asynchronous or synchronous mode can be selected by configuring SYNC in USARTn_CTRL. The options are listed with supported protocols in Table 16.1 (p. 177) . Full duplex and half duplex communication is supported in both asynchronous and synchronous mode. Table ...
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Table 16.3. USART Data Bits DATA BITS [3:0] 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Table 16.4. USART Stop Bits STOP BITS [1: The order in which the data bits ...
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Table 16.5. USART Parity Bits STOP BITS [1: 16.3.2.2 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Equation 16.1 (p. ...
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Table 16.7. USART Baud Rates @ 4MHz Peripheral Clock USARTn_OVS =00 Desired baud rate USARTn_CLKDIV/256 [baud/s] 600 415,75 1200 207,25 2400 103,25 4800 51 9600 25 14400 16,25 19200 12 28800 7,75 38400 5,5 57600 3,25 76800 2,25 115200 1,25 ...
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When data is written to the transmit buffer using USARTn_TXDATAX and USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override the value in BIT8DV in USARTn_CTRL, and alone define the ...
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Note When in SmartCard mode with repeat enabled, none of the actions, except generate break, will be performed until the frame is transmitted without failure. Generation of a break in SmartCard mode with repeat enabled will cause the USART to ...
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Figure 16.4. USART Receive Buffer Operation RXDOUBLE RXDOUBLEX RX buffer elem ent 0 RXDOUBLEXP RX buffer elem ent 1 Shift register The receive buffer, including the receive shift register can be cleared by setting CLEARRX in USARTn_CMD. Any frame currently ...
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Figure 16.5 (p. 184) . With OVS=0 in USARTn_CTRL, the start and data bits are thus sampled at locations 8, 9 and 10 in the figure, locations 4, 5 and 6 for OVS=1 and locations 3, 4, and 5 for ...
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When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices. In this case, the stop-bit is not sampled, and no framing error is generated in the receiver if the stop- bit is ...
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Single Data-link In this setup, the USART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in USARTn_CTRL, which connects the receiver to the transmitter output. Because they are both connected to the ...
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The USn_CS output is active low by default, but its polarity can be changed with CSINV in USARTn_CTRL. AUTOCS works regardless of which mode the USART is in, so this functionality can also be used for automatic chip/slave select when ...
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Figure 16.10. USART Transmission of Large Frames, MSBF TX buffer elem ent 1 TX buffer elem ent Figure 16.10 (p. 188) illustrates the order of the transmitted bits when an 11 bit frame ...
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MPAF interrupt flag in USARTn_IF is set, and the address frame is loaded into the receive register. This happens regardless of the value of RXBLOCK in USARTn_STATUS. Multi-processor mode is enabled by setting MPM in USARTn_CTRL, and the value of ...
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USARTn_CTRL or through an external connection. The TX output should be configured as open-drain in the GPIO module. When no parity error is identified by the receiver, the data frame is as shown in Figure 16.12 (p. 190) . The ...
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Figure 16.14. USART SmartCard Stop Bit Sampling 1/2 stop bit For communication with a SmartCard, a clock signal needs to be generated ...
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USART Synchronous Mode Clock Division Factor USARTn_CLKDIV = 256 x (f When the USART operates in master mode, the highest possible bit rate is half the peripheral clock rate. When operating in slave mode however, the highest bit rate is ...
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Communication starts whenever there is data in the transmit buffer and the transmitter is enabled. The USART clock then starts, and the master shifts bits out from the transmit shift register using the internal clock. When there are no more ...
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When operating as SPI slave in half duplex mode, TX has to be tristated (not disabled) during data reception if the slave is to transmit data in the current transfer. 16.3.4 PRS-triggered Transmissions If a transmission must be started on ...
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Separating the interrupts in this way allows different priorities to be set for transmission and reception interrupts. The transmission interrupt vector groups the transmission-related interrupts generated by the following interrupt flags: • TXC • TXBL • TXOF • ...
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Table 16.9. USART IrDA Pulse Widths IRPW Pulse width OVS=0 00 1/16 01 2/16 10 3/16 11 4/16 By default, no filter is enabled in the IrDA demodulator. A filter can be enabled by setting IRFILT in USARTn_IRCTRL. When the ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 USARTn_CTRL 0x004 USARTn_FRAME 0x008 USARTn_TRIGCTRL 0x00C USARTn_CMD 0x010 USARTn_STATUS 0x014 USARTn_CLKDIV 0x018 USARTn_RXDATAX 0x01C USARTn_RXDATA 0x020 USARTn_RXDOUBLEX 0x024 USARTn_RXDOUBLE 0x028 USARTn_RXDATAXP 0x02C USARTn_RXDOUBLEXP ...
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Bit Name Reset 27:26 TXDELAY 0x0 Configurable delay before new transfers. Frames sent back-to-back are not delayed. Value Mode 0 NONE 1 SINGLE 2 DOUBLE 3 TRIPLE 25 Reserved To ensure compatibility with future devices, always write bits to 0. ...
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Bit Name Reset Value Description 0 Output from the transmitter is passed unchanged to U(S)n_TX 1 Output from the transmitter is inverted before it is passed to U(S)n_TX 13 RXINV 0 Setting this bit will invert the input to the ...
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Bit Name Reset Multi-processor mode uses the 9th bit of the USART frames to tell whether the frame is an address frame or a data frame. Value Description 0 The 9th bit of incoming frames has no special function 1 ...