EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 432

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

29.4 Register Map
29.5 Register Description
29.5.1 LCD_CTRL - Control Register (Async Reg)
31:3
2:1
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
0x060
0x064
Offset
0x000
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
UDCTRL
These bits control how data from the SEGDn registers are transferred to the LCD driver.
Name
Value
0
1
Name
LCD_CTRL
LCD_DISPCTRL
LCD_SEGEN
LCD_BACTRL
LCD_STATUS
LCD_AREGA
LCD_AREGB
LCD_IF
LCD_IFS
LCD_IFC
LCD_IEN
LCD_SEGD0L
LCD_SEGD1L
LCD_SEGD2L
LCD_SEGD3L
LCD_SEGD0H
LCD_SEGD1H
LCD_SEGD2H
LCD_SEGD3H
LCD_FREEZE
LCD_SYNCBUSY
Mode
REGULAR
FCEVENT
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
Access
Description
The data transfer is controlled by SW. Transfer is performed as soon as possible
The data transfer is done at the next event triggered by the Frame Counter
...the world's most energy friendly microcontrollers
432
Bit Position
Type
RW
RW
RW
RW
R
RW
RW
R
W1
W1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Update Data Control
Description
Description
Control Register
Display Control Register
Segment Enable Register
Blink and Animation Control Register
Status Register
Animation Register A
Animation Register B
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
Segment Data Low Register 0
Segment Data Low Register 1
Segment Data Low Register 2
Segment Data Low Register 3
Segment Data High Register 0
Segment Data High Register 1
Segment Data High Register 2
Segment Data High Register 3
Freeze Register
Synchronization Busy Register
www.energymicro.com