EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 313

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.4 Register Map
22.5 Register Description
22.5.1 PCNTn_CTRL - Control Register (Async Reg)
31:6
5
4
3
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
Offset
0x000
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
RSTEN
The PCNT clock domain is asynchronously held in reset when this bit is set. The reset is synchronously released two PCNT clock
edges after this bit is cleared. If external clock used the reset should be performed by setting and clearing the bit without pending
for SYNCBUSY bit.
FILT
The filter passes all high and low periods that are at least 5 clock cycles long. This filter is only available on OVSSINGLE mode.
EDGE
Determines the polarity of the incoming edges. This bit should be written when PCNT is in DISABLE mode, otherwise the behavior
is unpredictable. This bit is ignored in EXTCLKSINGLE mode.
Name
Value
0
1
Name
PCNTn_CTRL
PCNTn_CMD
PCNTn_STATUS
PCNTn_CNT
PCNTn_TOP
PCNTn_TOPB
PCNTn_IF
PCNTn_IFS
PCNTn_IFC
PCNTn_IEN
PCNTn_ROUTE
PCNTn_FREEZE
PCNTn_SYNCBUSY
Mode
POS
NEG
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
Access
Description
Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode.
Negative edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode, and
the counter direction is inverted in EXTCLKQUAD mode.
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313
Bit Position
Type
RW
W1
R
R
R
RW
R
W1
W1
RW
RW
RW
R
Enable PCNT Clock Domain Reset
Enable Digital Pulse Width Filter
Edge Select
Description
Description
Control Register
Command Register
Status Register
Counter Value Register
Top Value Register
Top Value Buffer Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
I/O Routing Register
Freeze Register
Synchronization Busy Register
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