EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 173

MCU 32BIT 16KB FLASH 32-QFN

EFM32G200F16

Manufacturer Part Number
EFM32G200F16
Description
MCU 32BIT 16KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F16

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
15.5.15 I2Cn_ROUTE - I/O Routing Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
31:10
Bit
Offset
0x038
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
CLTO
Enable interrupt on clock low timeout.
BITO
Enable interrupt on bus idle timeout.
RXUF
Enable interrupt on receive buffer underflow.
TXOF
Enable interrupt on transmit buffer overflow.
BUSHOLD
Enable interrupt on bus-held.
BUSERR
Enable interrupt on bus error.
ARBLOST
Enable interrupt on loss of arbitration.
MSTOP
Enable interrupt on MSTOP.
NACK
Enable interrupt when not-acknowledge is received.
ACK
Enable interrupt on acknowledge received.
RXDATAV
Enable interrupt on receive buffer full.
TXBL
Enable interrupt on transmit buffer level.
TXC
Enable interrupt on transfer completed.
ADDR
Enable interrupt on recognized address.
RSTART
Enable interrupt on transmitted or received repeated START condition.
START
Enable interrupt on transmitted or received START condition.
Reserved
Name
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
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173
Bit Position
Clock Low Interrupt Enable
Bus Idle Timeout Interrupt Enable
Receive Buffer Underflow Interrupt Enable
Transmit Buffer Overflow Interrupt Enable
Bus Held Interrupt Enable
Bus Error Interrupt Enable
Arbitration Lost Interrupt Enable
MSTOP Interrupt Enable
Not Acknowledge Received Interrupt Enable
Acknowledge Received Interrupt Enable
Receive Data Valid Interrupt Enable
Transmit Buffer level Interrupt Enable
Transfer Completed Interrupt Enable
Address Interrupt Enable
Repeated START condition Interrupt Enable
START Condition Interrupt Enable
Description
Description
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