EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 119

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12 WDOG - Watchdog Timer
12.1 Introduction
12.2 Features
12.3 Functional Description
2010-09-06 - d0001_Rev1.00
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase
application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or
by a software failure.
• Clock input from selectable oscillators
• Configurable timeout period from 9 to 256k watchdog clock cycles
• Individual selection to keep running or freeze when entering EM2 or EM3
• Selection to keep running or freeze when entering debug mode
• Selection to block the CPU from entering Energy Mode 4
• Selection to block the CMU from disabling the selected watchdog clock
The watchdog is enabled by setting the EN bit in WDOG_CTRL. When enabled, the watchdog counts
up to the period value configured through the PERSEL field in WDOG_CTRL. If the watchdog timer is
not cleared to 0(by writing a 1 to the CLEAR bit in WDOG_CMD) before the period is reached, the chip
is reset. If a timely clear command is issued, the timer starts counting up from 0 again. The watchdog
can optionally be locked by writing the LOCK bit in WDOG_CTRL. Once locked, it cannot be disabled
or reconfigured by software.
The watchdog counter is reset when EN is reset.
0 1 2 3
• Internal 32.768 kHz RC oscillator
• Internal 1kHz RC oscillator
• External 32.768 kHz XTAL oscillator
Tim eout period
4
Counter value
Watchdog clear
System reset
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119
Tim e
What?
The WDOG (Watchdog Timer) resets the
system in case of a fault condition, and can
be enabled in all energy modes as long as
the low frequency clock source is available.
Why?
If a software failure or external event renders
the MCU unresponsive, a Watchdog timeout
will reset the system to a known, safe state.
How?
An enabled Watchdog Timer implements a
configurable timeout period. If the CPU fails
to re-start the Watchdog Timer before it times
out, a full system reset will be triggered. The
Watchdog consumes insignificant power,
and allows the device to remain safely in low
energy modes for up to 256 seconds at a
time.
Quick Facts
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