EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 154

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-09-06 - d0001_Rev1.00
As when operating as a master transmitter, arbitration can be lost as a master receiver. When this
happens the ARBLOST interrupt flag in I2Cn_IF is set, and the master has a possibility of being selected
as a slave given the correct conditions.
Table 15.5. I
I2Cn_STATE Description
0x57
0x57
-
0x93
0x9B
0xB3
-
START transmitted
Repeated START
transmitted
ADDR+R transmitted
ADDR+R transmitted,
ACK received
ADDR+R
transmitted,NACK
received
Data received
Stop received
2
C Master Receiver
I2Cn_IF
START interrupt flag
(BUSHOLD interrupt
flag)
START interrupt
flag(BUSHOLD
interrupt flag)
TXBL interrupt flag
(TXC interrupt flag)
ACK interrupt
flag(BUSHOLD)
NACK(BUSHOLD)
RXDATA interrupt
flag(BUSHOLD
interrupt flag)
MSTOP interrupt flag
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154
Required
interaction
ADDR
+R ->
TXDATA
STOP
STOP +
START
ADDR
+R ->
TXDATA
STOP
STOP +
START
None
RXDATA
STOP
START
STOP +
START
CONT +
RXDATA
STOP
START
STOP +
START
ACK +
RXDATA
NACK +
CONT +
RXDATA
ACK/
NACK +
STOP
ACK/
NACK +
START
ACK/
NACK +
STOP +
START
None
Response
ADDR+R will be sent
STOP will be sent and bus released.
STOP will be sent and bus released. Then a
START will be sent when bus becomes idle.
ADDR+R will be sent
STOP will be sent and bus released.
STOP will be sent and bus released. Then a
START will be sent when bus becomes idle.
Start receiving
STOP will be sent and the bus released
Repeated START will be sent
STOP will be sent and the bus released. Then
a START will be sent when the bus becomes
idle
Continue, start receiving
STOP will be sent and the bus released
Repeated START will be sent
STOP will be sent and the bus released. Then
a START will be sent when the bus becomes
idle
ACK will be transmitted, reception continues
NACK will be transmitted, reception continues
ACK/NACK will be sent and the bus will be
released.
ACK/NACK will be sent, and then a repeated
start condition.
ACK/NACK will be sent and the bus will be
released. Then a START will be sent when the
bus becomes idle
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