EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 208

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
31:8
7:0
31
30
29
28
27
26:25
24:16
15
14
13
12
11
10:9
8:0
Bit
Offset
0x038
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
TXDATA
This frame will be added to TX buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.
RXENAT1
Set to enable reception after transmission.
TXDISAT1
Set to disable transmitter and release data bus directly after transmission.
TXBREAK1
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of USARTn_WDATA.
TXTRIAT1
Set to tristate transmitter by setting TXTRI after transmission.
UBRXAT1
Set clear RXBLOCK after transmission, unblocking the receiver.
Reserved
TXDATA1
Second frame to write to FIFO.
RXENAT0
Set to enable reception after transmission.
TXDISAT0
Set to disable transmitter and release data bus directly after transmission.
TXBREAK0
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of WDATA.
TXTRIAT0
Set to tristate transmitter by setting TXTRI after transmission.
UBRXAT0
Set clear RXBLOCK after transmission, unblocking the receiver.
Reserved
TXDATA0
First frame to write to buffer.
Name
Name
0x00
0
0
0
0
0
0x000
0
0
0
0
0
0x000
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W
W
W
W
W
W
W
W
W
W
W
W
W
Access
Access
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208
Bit Position
TX Data
Enable RX After Transmission
Clear TXEN After Transmission
Transmit Data As Break
Set TXTRI After Transmission
Unblock RX After Transmission
TX Data
Enable RX After Transmission
Clear TXEN After Transmission
Transmit Data As Break
Set TXTRI After Transmission
Unblock RX After Transmission
TX Data
Description
Description
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