EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 368

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.4 Register Map
26.5 Register Description
26.5.1 DACn_CTRL - Control Register
31:22
21:20
19
18:16
15:14
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
Offset
0x000
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
Reserved
REFRSEL
Select refresh counter timeout value. A channel x will be refreshed with the interval set in this register if the REFREN bit in
DACn_CHxCTRL is set.
Reserved
PRESC
Select clock division factor.
LPFFREQ
Name
Value
0
1
2
3
Value
PRESC
Name
DACn_CTRL
DACn_STATUS
DACn_CH0CTRL
DACn_CH1CTRL
DACn_IEN
DACn_IF
DACn_IFS
DACn_IFC
DACn_CH0DATA
DACn_CH1DATA
DACn_COMBDATA
DACn_CAL
DACn_BIASPROG
Mode
8CYCLES
16CYCLES
32CYCLES
64CYCLES
0x0
0x0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
Access
Description
Clock division factor of 2^PRESC.
Description
All channels with enabled refresh are refreshed every 8 prescaled cycles
All channels with enabled refresh are refreshed every 16 prescaled cycles
All channels with enabled refresh are refreshed every 32 prescaled cycles
All channels with enabled refresh are refreshed every 64 prescaled cycles
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368
Bit Position
Type
RW
R
RW
RW
RW
R
W1
W1
RW
RW
W
RW
RW
Refresh Interval Select
Prescaler Setting
Low Pass Filter Cut-off Frequency
Description
Description
Control Register
Status Register
Channel 0 Control Register
Channel 1 Control Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Channel 0 Data Register
Channel 1 Data Register
Combined Data Register
Calibration Register
Bias Programming Register
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