EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 269

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.5.13 TIMERn_CCx_CCV - CC Channel Value Register
7:5
4
3
2
1:0
31:16
15:0
Bit
Offset
0x034
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
COIST
This bit is only used in Output Compare and PWM mode. When this bit is set in compare mode,the output is set high when the counter
is disabled. When counting resumes, this value will represent the initial value for the output. If the bit is cleared, the output will be
cleared when the counter is disabled. In PWM mode, the output will always be low when disabled, regardless of this bit. However,
this bit will represent the initial value of the output, once it is enabled.
Reserved
OUTINV
Setting this bit inverts the output from the CC channel (Output compare,PWM).
MODE
These bits select the mode for Compare/Capture channel.
Reserved
CCV
In input capture mode, this field holds the first unread capture value. When reading this register in input capture mode, then contents
of the TIMERn_CCx_CCVB register will be written to TIMERn_CCx_CCV in the next cycle. In compare mode, this fields holds the
compare value.
Name
Name
Value
3
Value
0
1
2
3
Mode
SET
Mode
OFF
INPUTCAPTURE
OUTPUTCOMPARE
PWM
0
0
0x0
0x0000
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RWH
Access
Access
Description
Set output on compare match
Description
Compare/Capture channel turned off
Input capture
Output compare
Pulse-Width Modulation
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269
Bit Position
Compare Output Initial State
Output Invert
CC Channel Mode
CC Channel Value
Description
Description
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