EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 204

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register
16.5.8 USARTn_RXDATA - RX Buffer Data Register
31:21
20:6
5:0
31:16
15
14
13:9
8:0
31:8
7:0
Bit
Offset
0x018
Reset
Access
Name
Bit
Offset
0x01C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
DIV
Specifies the fractional clock divider for the USART.
Reserved
Reserved
FERR
Set if data in buffer has a framing error. Can be the result of a break condition.
PERR
Set if data in buffer has a parity error (asynchronous mode only).
Reserved
RXDATA
Use this register to access data read from the USART. Buffer is cleared on read access.
Reserved
RXDATA
Use this register to access data read from USART. Buffer is cleared on read access. Only the 8 LSB can be read using this register.
Name
Name
Name
0x0000
0
0
0x000
0x00
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
R
R
R
R
Access
Access
Access
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204
Bit Position
Bit Position
Fractional Clock Divider
Data Framing Error
Data Parity Error
RX Data
RX Data
Description
Description
Description
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