EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 239

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)
18.5.17 LEUARTn_FREEZE - Freeze Register
4
3
2
1
0
31:6
5
4
3:0
Bit
Offset
0x03C
Reset
Access
Name
Bit
Offset
0x040
Reset
Access
Name
2010-09-06 - d0001_Rev1.00
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
RXUF
Enable interrupt on RX underflow.
RXOF
Enable interrupt on RX overflow.
RXDATAV
Enable interrupt on RX data.
TXBL
Enable interrupt on TX buffer level.
TXC
Enable interrupt on TX complete.
Reserved
PULSEFILT
Enable a one-cycle pulse filter for pulse extender
PULSEEN
Filter LEUART output through pulse generator and the LEUART input through the pulse extender.
PULSEW
Configure the pulse width of the pulse generator as a number of 32.768 kHz clock cycles.
Name
Name
Value
0
1
Description
Filter is disabled. Pulses must be at least 2 cycles long for reliable detection.
Filter is enabled. Pulses must be at least 3 cycles long for reliable detection.
0
0
0
0
0
0
0
0x0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
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239
Bit Position
Bit Position
RX Underflow Interrupt Enable
RX Overflow Interrupt Enable
RX Data Valid Interrupt Enable
TX Buffer Level Interrupt Enable
TX Complete Interrupt Enable
Pulse Filter
Pulse Generator/Extender Enable
Pulse Width
Description
Description
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