EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 364

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.3.1.5 Clock Prescaling
26.3.2 Reference Selection
26.3.3 Programming of Bias Current
2010-09-06 - d0001_Rev1.00
a combined data register, DACn_COMBDATA, where the data values for both channels can be written
simultaneously. Writing to this register will start all enabled channels.
If the PRSEN bit in DACn_CHxCTRL is set, a DAC conversion on channel x will not be started by data
write, but when a positive one HFPERCLK cycle pulse is received on the PRS input selected by PRSSEL
in DACn_CHxCTRL.
The CH0DV and CH1DV bits in DACn_STATUS indicate that the corresponding channel contains data
that has not yet been converted.
When entering Energy Modes 2,3 or 4, both DAC channels should be stopped.
If the DAC is enabled for the first time after entering Energy Mode 2,3 the output of the DAC will be
undefined. One way of avoiding this is to make sure the DAC has been enabled before going into EM2/
EM3 the first time. Another option is to enable the DAC with output disabled and write a value to the
DAC output registers before enabling the DAC output.
The DAC has an internal clock prescaler, which can divide the HFPERCLK by any factor between 1 and
128, by setting the PRESC bits in DACnCTRL. The resulting DAC_CLK is used by the converter core
and the frequency is given by Equation 26.1 (p. 364) :
DAC Clock Prescaling
where f
DAC_CLK should not be set higher than 1 MHz.
Normally the PRESCALER runs continuously when either of the channels are enabled. When running
with a prescaler setting higher than 0, there will be an unpredictable delay from the time the conversion
was triggered to the time the actual conversion takes place. This is because the conversions is controlled
by the prescaled clock and the conversion can arrive at any time during a prescaled clock (DAC_CLK)
period. However, if the CH0PRESCRST bit in DACn_CTRL is set, the prescaler will be reset every time
a conversion is triggered on channel 0. This leads to a predictable latency between channel 0 trigger
and conversion.
Three internal voltage references are available and are selected by setting the REFSEL bits in
DACn_CTRL:
• Internal 2.5V
• Internal 1.25V
• V
The reference selection can only be changed while both channels are disabled. The references for the
DAC need to be enabled for some time before they can be used. This is called the warm-up period,
and starts when one of the channels is enabled. For a bandgap reference, this period is 5 DAC_CLK
cycles while the V
(given that the prescaler is set correctly) and delay any conversion triggers received during the warm-
up until the references have stabilized.
The bias current of the bandgap reference and the DAC output buffer can be scaled by the BIASPROG
and HALFBIAS bit fields of the DACn_BIASPROG register as illustrated in Figure 26.2 (p. 365) .
DD
HFPERCLK
is the HFPERCLK frequency. One conversion takes 2 DAC_CLK cycles and the
DD
reference needs 1 DAC_CLK cycle. The DAC will time this period automatically
f
DAC_CLK
= f
HFPERCLK
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364
/ 2 ^ PRESC
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(26.1)