EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 433

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

29.5.2 LCD_DISPCTRL - Display Control Register
0
31:21
20:18
17
16
15
14:13
12:8
7:5
Bit
Offset
0x004
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
EN
When this bit is set, the LCD driver is enabled and the driver will start outputting waveforms on the com/segment lines.
Reserved
VBLEV
These bits control Voltage Boost level. Please refer to datasheet for further details of the boost levels.
Reserved
VLCDSEL
This bit controls which Voltage source that is connected to V
CONCONF
This bit selects whether the contrast adjustment is done relative to V
Reserved
CONLEV
These bits control the contrast setting according to this formula: V
Reserved
Name
Name
Value
2
Value
0
1
2
3
4
5
6
7
Value
0
1
Value
0
1
Value
0
31
Mode
FRAMESTART
Mode
LEVEL0
LEVEL1
LEVEL2
LEVEL3
LEVEL4
LEVEL5
LEVEL6
LEVEL7
Mode
VDD
VEXTBOOST
Mode
VLCD
GND
Mode
MIN
MAX
0
0x3
0
0
0x1F
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
Access
Access
Description
The data transfer is done continously at every LCD frame start
Description
Minimum boost level
Maximum boost level
Description
VDD
Voltage Booster/External VDD
Description
Contrast is adjusted relative to V
Contrast is adjusted relative to Ground
Description
Minimum contrast
Maximum contrast
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433
Bit Position
LCD
LCD Enable
Voltage Boost Level
V
Contrast Configuration
Contrast Level
Description
Description
LCD
.
LCD_OUT
Selection
LCD
or Ground.
= V
LCD
× 0.5(1+CONLEV/31).
LCD
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