EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 70

MCU 32BIT 16KB FLASH 32-QFN

EFM32G200F16

Manufacturer Part Number
EFM32G200F16
Description
MCU 32BIT 16KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F16

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
8.7.18 DMA_IF - Interrupt Flag Register
8.7.19 DMA_IFS - Interrupt Flag Set Register
31
30:8
7
6
5
4
3
2
1
0
31
30:8
7
Offset
0x1000
Reset
Access
Name
Bit
Offset
0x1004
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
ERR
This flag is set when an error has occurred on the AHB bus.
Reserved
CH7DONE
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH6DONE
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH5DONE
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH4DONE
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH3DONE
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH2DONE
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH1DONE
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
CH0DONE
Set when the DMA channel has completed its transfer. If the channel is disabled, the flag is set when there is a request for the channel.
ERR
Set to 1 to set DMA error interrupt flag.
Reserved
CH7DONE
Write to 1 to set the corresponding DMA channel complete interrupt flag.
Name
Name
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
R
R
R
R
R
R
W1
W1
Access
Access
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Bit Position
Bit Position
70
DMA Error Interrupt Flag
DMA Channel 7 Complete Interrupt Flag
DMA Channel 6 Complete Interrupt Flag
DMA Channel 5 Complete Interrupt Flag
DMA Channel 4 Complete Interrupt Flag
DMA Channel 3 Complete Interrupt Flag
DMA Channel 3 Complete Interrupt Flag
DMA Channel 2 Complete Interrupt Flag
DMA Channel 1 Complete Interrupt Flag
DMA Error Interrupt Flag Set
DMA Channel 7 Complete Interrupt Flag Set
Description
Description
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