EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 55

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-09-06 - d0001_Rev1.00
Bit
[13:4]
[3]
[2:0]
Name
n_minus_1
next_useburst
cycle_ctrl
Description
Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers
that the DMA cycle contains. You must set these bits according to the size of DMA cycle that
you require.
The 10-bit value indicates the number of DMA transfers, minus one. The possible values are:
b000000000 = 1 DMA transfer
b000000001 = 2 DMA transfers
b000000010 = 3 DMA transfers
b000000011 = 4 DMA transfers
b000000100 = 5 DMA transfers
b111111111 = 1024 DMA transfers.
The controller updates this field immediately prior to it entering the arbitration process. This
enables the controller to store the number of outstanding DMA transfers that are necessary to
complete the DMA cycle.
Controls if the chnl_useburst_set [C] bit is set to a 1, when the controller is performing a
peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure.
Note
In peripheral scatter-gather DMA cycle then after the DMA cycle that uses the alternate data
structure completes , either:
0 = the controller does not change the value of the chnl_useburst_set [C] bit. If the
chnl_useburst_set [C] bit is 0 then for all the remaining DMA cycles in the peripheral scatter-
gather transaction, the controller responds to requests on dma_req[ ] and dma_sreq[ ],
when it performs a DMA cycle that uses an alternate data structure.
1 = the controller sets the chnl_useburst_set [C] bit to a 1. Therefore, for the remaining DMA
cycles in the peripheral scatter-gather transaction, the controller only responds to requests on
dma_req[ ], when it performs a DMA cycle that uses an alternate data structure.
The operating mode of the DMA cycle. The modes are:
b000
b001
b010
b011
b100
b101
b110
b111
.
.
.
Stop. Indicates that the data structure is invalid.
Basic. The controller must receive a new request, prior to it entering the arbitration
process, to enable the DMA cycle to complete.
Auto-request. The controller automatically inserts a request for the appropriate channel
during the arbitration process. This means that the initial request is sufficient to enable
the DMA cycle to complete.
Ping-pong. The controller performs a DMA cycle using one of the data structures. After
the DMA cycle completes, it performs a DMA cycle using the other data structure. After
the DMA cycle completes and provided that the host processor has updated the original
data structure, it performs a DMA cycle using the original data structure. The controller
continues to perform DMA cycles until it either reads an invalid data structure or the
host processor changes the cycle_ctrl bits to b001 or b010. See Section 8.4.2.3.4 (p.
43) .
Memory scatter/gather. See Section 8.4.2.3.5 (p. 45) .
When the controller operates in memory scatter-gather mode, you must only use this
value in the primary data structure.
Memory scatter/gather. See Section 8.4.2.3.5 (p. 45) .
When the controller operates in memory scatter-gather mode, you must only use this
value in the alternate data structure.
Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 48) .
When the controller operates in peripheral scatter-gather mode, you must only use this
value in the primary data structure.
Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 48) .
Immediately prior to completion of the DMA cycle that the alternate data structure
specifies, the controller sets the chnl_useburst_set [C] bit to 0 if the number of
remaining transfers is less than 2
controller performs an additional modification of the chnl_useburst_set [C] bit.
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R
. The setting of the next_useburst bit controls if the
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