EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 11

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.3 Functional Description
4.3.1 Interrupt Operation
2010-09-06 - d0001_Rev1.00
• Unaligned data storage and access
• Integrated power modes
• Optimized for low latency, nested interrupts
For a full functional description of the ARM Cortex-M3 implementation in the EFM32G family, the reader
is referred to the EFM32G Cortex-M3 Reference Manual.
Figure 4.1. Interrupt Operation
The EFM32G devices have up to 31 interrupt request lines (IRQ) which are connected to the Cortex-
M3. Each of these lines (shown in Table 4.1 (p. 12) ) is connected to one or more interrupt flags
in one or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also
possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified
with its own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to
generate the IRQ. A high IRQ line will set the corresponding pending bit (can also be set/cleared with
the SETPEND/CLRPEND bits in ISPR0/ICPR0) in the Cortex-M3 NVIC. The pending bit is then qualified
with a an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an
interrupt request to the core. Figure 4.1 (p. 11) illustrates the interrupt system. For more information
on how the interrupts are handled inside the Cortex-M3, the reader is referred to the EFM32G Cortex-
M3 Reference Manual.
Module
• Continuous storage of data requiring different byte lengths
• Data access in a single core access cycle
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
condition
Interrupt
IFS[ n]
IFC[ n]
set
IF[ n]
clear
IEN[ n]
IRQ
Cortex-M3 NVIC
...the world's most energy friendly microcontrollers
11
set
Software generated interrupt
SETPEND[ n] /CLRPEND[ n]
SETENA[ n] /CLRENA[ n]
Active interrupt
clear
Interrupt
request
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