EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 231

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.2 LEUARTn_CMD - Command Register (Async Reg)
3:2
1
0
31:8
7
6
5
4
3
2
1
0
Bit
Offset
0x004
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
PARITY
Determines whether parity bits are enabled, and whether even or odd parity should be used.
DATABITS
This register sets the number of data bits.
AUTOTRI
When set, LEUn_TX is tristated whenever the transmitter is inactive.
Reserved
CLEARRX
Set to clear receive buffer and the RX shift register.
CLEARTX
Set to clear transmit buffer and the TX shift register.
RXBLOCKDIS
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
RXBLOCKEN
Set to set RXBLOCK, resulting in all incoming frames being discarded.
TXDIS
Set to disable transmission.
TXEN
Set to enable data transmission.
RXDIS
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
RXEN
Name
Name
Value
0
2
3
Value
0
1
Value
0
1
Mode
NONE
EVEN
ODD
Mode
EIGHT
NINE
Description
LEUn_TX is held high when the transmitter is inactive. INV inverts the inactive state.
LEUn_TX is tristated when the transmitter is inactive
0x0
0
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
W1
W1
W1
W1
W1
W1
W1
W1
Access
Access
Description
Parity bits are not used
Even parity are used. Parity bits are automatically generated and checked by hardware.
Odd parity is used. Parity bits are automatically generated and checked by hardware.
Description
Each frame contains 8 data bits
Each frame contains 9 data bits
...the world's most energy friendly microcontrollers
231
Bit Position
Parity-Bit Mode
Data-Bit Mode
Automatic Transmitter Tristate
Clear RX
Clear TX
Receiver Block Disable
Receiver Block Enable
Transmitter Disable
Transmitter Enable
Receiver Disable
Receiver Enable
Description
Description
www.energymicro.com