EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 166

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.3 I2Cn_STATE - State Register
15.5.4 I2Cn_STATUS - Status Register
31:8
7:5
4
3
2
1
0
31:9
Offset
0x008
Reset
Access
Name
Bit
Offset
0x00C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
STATE
The state of any current transmission. Cleared if the I
BUSHOLD
Set if the bus is currently being held by this I
NACKED
Set if a NACK was received and STATE is ADDRACK or DATAACK.
TRANSMITTER
Set when operating as a master transmitter or a slave transmitter. When cleared, the system may be operating as a master receiver,
a slave receiver or the current mode is not known.
MASTER
Set when operating as an I
BUSY
Set when the bus is busy. Whether the I
MCU comes out of reset, the state of the bus is not known, and thus BUSY is set. Use the ABORT command or a bus idle timeout
to force the I
Reserved
Name
Name
Value
0
1
2
3
4
5
6
2
C module out of the BUSY state.
Mode
IDLE
WAIT
START
ADDR
ADDRACK
DATA
DATAACK
2
C master. When cleared, the system may be operating as an I
0x0
0
0
0
0
1
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
C module is in control of the bus or not has no effect on the value of this bit. When the
2
C module.
R
R
R
R
R
R
Access
Access
2
C module is idle.
Description
No transmission is being performed.
Waiting for idle. Will send a start condition as soon as the bus is idle.
Start transmitted or received
Address transmitted or received
Address ack/nack transmitted or received
Data transmitted or received
Data ack/nack transmitted or received
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166
Bit Position
Bit Position
Transmission State
Bus Held
Nack Received
Transmitter
Master
Bus Busy
Description
Description
2
C slave.
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