EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 271

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.5.17 TIMERn_DTTIME - DTI Time Control Register
31:25
24
23:7
6:4
3
2
1
0
31:22
21:16
15:14
13:8
Bit
Offset
0x074
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
DTPRSEN
Enable/disable PRS as DTI input.
Reserved
DTPRSSEL
Select which PRS channel to listen to.
DTCINV
Set to invert complementary outputs.
DTIPOL
Set inactive polarity for outputs.
DTDAS
Configure DTI restart on debugger exit.
DTEN
Enable/disable DTI.
Reserved
DTFALLT
Set time span for the falling edge.
Reserved
DTRISET
Name
Name
Value
0
1
2
3
4
5
6
7
Value
0
1
Value
DTFALLT
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
Mode
NORESTART
RESTART
0
0x0
0
0
0
0
0x00
0x00
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
Description
Fall time of DTFALLT+1 prescaled HFPERCLK cycles
Description
PRS Channel 0 selected as input
PRS Channel 1 selected as input
PRS Channel 2 selected as input
PRS Channel 3 selected as input
PRS Channel 4 selected as input
PRS Channel 5 selected as input
PRS Channel 6 selected as input
PRS Channel 7 selected as input
Description
No DTI restart on debugger exit
DTI restart on debugger exit
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271
Bit Position
DTI PRS Source Enable
DTI PRS Source Channel Select
DTI Complementary Output Invert.
DTI Inactive Polarity
DTI Automatic Start-up Functionality
DTI Enable
DTI Fall-time
DTI Rise-time
Description
Description
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