EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 229

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.4 Register Map
18.5 Register Description
18.5.1 LEUARTn_CTRL - Control Register (Async Reg)
31:16
15:14
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x054
Offset
0x000
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
TXDELAY
Configurable delay before new transfers. Frames sent back-to-back are not delayed.
Name
Value
0
1
2
3
Name
LEUARTn_CTRL
LEUARTn_CMD
LEUARTn_STATUS
LEUARTn_CLKDIV
LEUARTn_STARTFRAME
LEUARTn_SIGFRAME
LEUARTn_RXDATAX
LEUARTn_RXDATA
LEUARTn_RXDATAXP
LEUARTn_TXDATAX
LEUARTn_TXDATA
LEUARTn_IF
LEUARTn_IFS
LEUARTn_IFC
LEUARTn_IEN
LEUARTn_PULSECTRL
LEUARTn_FREEZE
LEUARTn_SYNCBUSY
LEUARTn_ROUTE
Mode
NONE
SINGLE
DOUBLE
TRIPLE
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
Access
Description
Frames are transmitted immediately
Transmission of new frames are delayed by a single baud period
Transmission of new frames are delayed by two baud periods
Transmission of new frames are delayed by three baud periods
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229
Bit Position
Type
RW
W1
R
RW
RW
RW
R
R
R
W
W
R
W1
W1
RW
RW
RW
R
RW
TX Delay Transmission
Description
Description
Control Register
Command Register
Status Register
Clock Control Register
Start Frame Register
Signal Frame Register
Receive Buffer Data Extended Register
Receive Buffer Data Register
Receive Buffer Data Extended Peek Register
Transmit Buffer Data Extended Register
Transmit Buffer Data Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
Pulse Control Register
Freeze Register
Synchronization Busy Register
I/O Routing Register
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