EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 194

MCU 32BIT 16KB FLASH 32-QFN

EFM32G200F16

Manufacturer Part Number
EFM32G200F16
Description
MCU 32BIT 16KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F16

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
16.3.4 PRS-triggered Transmissions
16.3.5 DMA Support
16.3.6 Transmission Delay
16.3.7 Interrupts
2010-09-06 - d0001_Rev1.00
If a transmission must be started on an event with very little delay, the PRS system can be used
to trigger the transmission. The PRS channel to use as a trigger can be selected using TSEL in
USARTn_TRIGCTRL. When a positive edge is detected on this signal, the receiver is enabled if RXTEN
in USARTn_TRIGCTRL is set, and the transmitter is enabled if TXTEN in USARTn_TRIGCTRL is set.
Only one signal input is supported by the USART.
The USART has full DMA support. The DMA controller can write to the transmit buffer using the
registers USARTn_TXDATA, USARTn_TXDATAX, USARTn_TXDOUBLE and USARTn_TXDOUBLEX,
and it can read from the receive buffer using the registers USARTn_RXDATA, USARTn_RXDATAX,
USARTn_RXDOUBLE and USARTn_RXDOUBLEX. This enables single byte transfers, 9 bit data +
control/status bits, double byte and double byte + control/status transfers both to and from the USART.
A request for the DMA controller to read from the USART receive buffer can come from the following
source:
• Data available in the receive buffer
• Data available in the receive buffer and data is for the RIGHT I2S channel. Only used in I2S mode.
A write request can come from one of the following sources:
• Transmit buffer and shift register empty. No data to send.
• Transmit buffer has room for more data
• Transmit buffer has room for RIGHT I2S data. Only used in I2S mode
Even though there are two sources for write requests to the DMA, only one should be used at a time,
since the requests from both sources are cleared even though only one of the requests are used.
In some cases, it may be sensible to temporarily stop DMA access to the USART when an error such
as a framing error has occurred. This is enabled by setting ERRSDMA in USARTn_CTRL.
By configuring TXDELAY in USARTn_CTRL, the transmitter can be forced to wait a number of bit-
periods from it is ready to transmit data, to it actually transmits the data. This delay is only applied to the
first frame transmitted after the transmitter has been idle. When transmitting frames back-to-back the
delay is not introduced between the transmitted frames.
This is useful on half duplex buses, because the receiver always returns received frames to software
during the first stop-bit. The bus may still be driven for up to 3 baud periods, depending on the current
frame format. Using the transmission delay, a transmission can be started when a frame is received,
and it is possible to make sure that the transmitter does not begin driving the output before the frame
on the bus is completely transmitted.
TXDELAY in USARTn_CTRL only applies to asynchronous transmission.
The interrupts generated by the USART are combined into two interrupt vectors. Interrupts related to
reception are assigned to one interrupt vector, and interrupts related to transmission are assigned to
When operating as SPI slave in half duplex mode, TX has to be tristated (not disabled)
during data reception if the slave is to transmit data in the current transfer.
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