EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 105

MCU 32BIT 16KB FLASH 32-QFN

EFM32G200F16

Manufacturer Part Number
EFM32G200F16
Description
MCU 32BIT 16KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F16

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
11.5.8 CMU_CALCNT - Calibration Counter Register
11.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register
31:20
19:0
31:10
9
8
7
6
5
4
3
Offset
0x01C
Reset
Access
Name
Bit
Offset
0x020
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
CALCNT
Write top value before calibration. Read calibration result from this register when Calibration Ready flag has been set.
Reserved
LFXODIS
Disables the LFXO. LFXOEN has higher priority if written simultaneously.
LFXOEN
Enables the LFXO.
LFRCODIS
Disables the LFRCO. LFRCOEN has higher priority if written simultaneously.
LFRCOEN
Enables the LFRCO.
AUXHFRCODIS
Disables the AUXHFRCO. AUXHFRCOEN has higher priority if written simultaneously. WARNING: Do not disable this clock during
a flash erase/write operation.
AUXHFRCOEN
Enables the AUXHFRCO.
HFXODIS
Disables the HFXO. HFXOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRXO if this oscillator
is selected as the source for HFCLK.
Name
Name
0x00000
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RWH
W1
W1
W1
W1
W1
W1
W1
Access
Access
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105
Bit Position
Bit Position
Calibration Counter
LFXO Disable
LFXO Enable
LFRCO Disable
LFRCO Enable
AUXHFRCO Disable
AUXHFRCO Enable
HFXO Disable
Description
Description
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