EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 238

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.15 LEUARTn_IEN - Interrupt Enable Register
31:11
10
9
8
7
6
5
4
3
2:1
0
31:11
10
9
8
7
6
5
Bit
Offset
0x038
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
SIGF
Write to 1 to clear the SIGF interrupt flag.
STARTF
Write to 1 to clear the STARTF interrupt flag.
MPAF
Write to 1 to clear the MPAF interrupt flag.
FERR
Write to 1 to clear the FERR interrupt flag.
PERR
Write to 1 to clear the PERR interrupt flag.
TXOF
Write to 1 to clear the TXOF interrupt flag.
RXUF
Write to 1 to clear the RXUF interrupt flag.
RXOF
Write to 1 to clear the RXOF interrupt flag.
Reserved
TXC
Write to 1 to clear the TXC interrupt flag.
Reserved
SIGF
Enable interrupt on signal frame.
STARTF
Enable interrupt on start frame.
MPAF
Enable interrupt on multi-processor address frame.
FERR
Enable interrupt on framing error.
PERR
Enable interrupt on parity error.
TXOF
Enable interrupt on TX overflow.
Name
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
W1
W1
W1
RW
RW
RW
RW
RW
RW
Access
Access
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238
Bit Position
Clear Signal-Frame Interrupt Flag
Clear Start-Frame Interrupt Flag
Clear Multi-Processor Address Frame Interrupt Flag
Clear Framing Error Interrupt Flag
Clear Parity Error Interrupt Flag
Clear TX Overflow Interrupt Flag
Clear RX Underflow Interrupt Flag
Clear RX Overflow Interrupt Flag
Clear TX Complete Interrupt Flag
Signal Frame Interrupt Enable
Start Frame Interrupt Enable
Multi-Processor Address Frame Interrupt Enable
Framing Error Interrupt Enable
Parity Error Interrupt Enable
TX Overflow Interrupt Enable
Description
Description
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