EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 152

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-09-06 - d0001_Rev1.00
value of I2Cn_STATE will then be 0x57. As seen in the table, the I
the address is not available after a repeated start condition.
To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 most significant bits
and the least significant bit cleared (ADDR+W). This address will then be transmitted, and the slave will
reply with an ACK or a NACK. If no slave replies to the address, the response will also be NACK. If
the address was acknowledged, the master now has four choices. If another byte is made available in
I2Cn_TXDATA, this byte is transmitted. The master can also stop the transmission by sending a STOP,
it can send a repeated start by sending START, or it can send a STOP and then a START as soon
as possible.
If a NACK was received, the master has to issue a CONT command in addition to providing data in order
to continue transmission. This is not standard I
are similar to when an ACK was received.
If a new byte was transmitted, an ACK or NACK is received after the transmission of the byte, and the
master has the same options as for when the address was sent.
The master may lose arbitration at any time during transmission. In this case, the ARBLOST interrupt flag
in I2Cn_IF is set. If the arbitration was lost during the transfer of an address, and SLAVE in I2Cn_CTRL
is set, the master then checks which address was transmitted. If it was the address of the master, then
the master goes to slave mode.
After a master has transmitted a START and won any arbitration, it owns the bus until it transmits a
STOP. After a STOP, the bus is released, and arbitration decides which bus master gains the bus next.
The MSTOP interrupt flag in I2Cn_IF is set when a STOP condition is transmitted by the master.
Table 15.4. I
I2Cn_STATE Description
0x57
0x57
-
0x97
0x9F
Start transmitted
Repeated start
transmitted
ADDR+W transmitted
ADDR+W transmitted,
ACK received
ADDR+W
transmitted,NACK
received
2
C Master Transmitter
I2Cn_IF
START interrupt flag
(BUSHOLD interrupt
flag)
START interrupt flag
(BUSHOLD interrupt
flag)
TXBL interrupt flag
(TXC interrupt flag)
ACK interrupt flag
(BUSHOLD interrupt
flag)
NACK (BUSHOLD
interrupt flag)
2
...the world's most energy friendly microcontrollers
C, but is provided for flexibility. The rest of the options
152
Required
interaction
ADDR
+W ->
TXDATA
STOP
STOP +
START
ADDR
+W ->
TXDATA
STOP
STOP +
START
None
TXDATA
STOP
START
STOP +
START
CONT +
TXDATA
STOP
Response
ADDR+W will be sent
STOP will be sent and bus released.
STOP will be sent and bus released. Then a
START will be sent when bus becomes idle.
ADDR+W will be sent
STOP will be sent and bus released.
STOP will be sent and bus released. Then a
START will be sent when bus becomes idle.
DATA will be sent
STOP will be sent. Bus will be released
Repeated start condition will be sent
STOP will be sent and the bus released. Then
a START will be sent when the bus becomes
idle
DATA will be sent
STOP will be sent. Bus will be released
2
C module also stops in this state if
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