EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 188

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.3.2.8 Multi-Processor Mode
2010-09-06 - d0001_Rev1.00
Figure 16.10. USART Transmission of Large Frames, MSBF
Figure 16.10 (p. 188) illustrates the order of the transmitted bits when an 11 bit frame is transmitted
with MSBF set. If MSBF is set and the frame is smaller than 10 bits, only the contents of transmit buffer
0 will be transmitted.
When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large
frame is split into the two buffer elements. If BYTESWAP is cleared, the least significant 8 bits of the
received frame are loaded into the first element of the receive buffer, and the remaining bits are loaded
into the second element, as shown in Figure 16.11 (p. 188) . The first byte read from the buffer thus
contains the 8 least significant bits. Set BYTESWAP to reverse the order.
The status bits are loaded into both elements of the receive buffer. The frame is not moved from the
receive shift register before there are two free spaces in the receive buffer.
Figure 16.11. USART Reception of Large Frames
The two buffer elements can be read at the same time using the USARTn_RXDOUBLE or
USARTn_RXDOUBLEX register. RXDATA0 then refers to buffer element 0 and RXDATA1 refers to
buffer element 1.
Large frames can be used in both asynchronous and synchronous modes.
To simplify communication between multiple processors, the USART supports a special multi-processor
mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining
8 bits is data or an address.
When multi-processor mode is enabled, an incoming 9-bit frame with the 9th bit equal to the value of
MPAB in USARTn_CTRL is identified as an address frame. When an address frame is detected, the
RX buffer elem ent 0
RX buffer elem ent 1
Status
TX buffer elem ent 1
TX buffer elem ent 0
2
1
0
Shift register
7
0
6
1
Status
Status
5
2
Peripheral Bus
4
3
0
0
3
4
1
1
Peripheral Bus
2
2
5
2
1
6
3
0
0
0
7
4
1
1
0
5
Shift register
...the world's most energy friendly microcontrollers
2
2
1
6
188
3
2
7
4
5
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7
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