EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 203

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.5 USARTn_STATUS - USART Status Register
16.5.6 USARTn_CLKDIV - Clock Control Register
31:9
8
7
6
5
4
3
2
1
0
Offset
0x010
Reset
Access
Name
Bit
Offset
0x014
Reset
Access
Name
2010-09-06 - d0001_Rev1.00
Reserved
RXFULL
Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one more
frame in the receive shift register.
RXDATAV
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
TXBL
Indicates the level of the transmit buffer. If TXBIL is cleared, TXBL is set whenever the transmit buffer is empty, and if TXBIL is set,
TXBL is set whenever the transmit buffer is half-full or empty.
TXC
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when data is written to the
transmit buffer.
TXTRI
Set when the transmitter is tristated, and cleared when transmitter output is enabled.
RXBLOCK
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the
instant the frame has been completely received.
MASTER
Set when the USART operates as a master. Set using the MASTEREN command and clear using the MASTERDIS command.
TXENS
Set when the transmitter is enabled.
RXENS
Set when the receiver is enabled.
Name
0
0
1
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
R
R
R
R
R
R
Access
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203
Bit Position
Bit Position
RX FIFO Full
RX Data Valid
TX Buffer Level
TX Complete
Transmitter Tristated
Block Incoming Data
SPI Master Mode
Transmitter Enable Status
Receiver Enable Status
Description
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