EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 236

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.12 LEUARTn_IF - Interrupt Flag Register
31:8
7:0
31:11
10
9
8
7
6
5
4
3
2
1
Offset
0x028
Reset
Access
Name
Bit
Offset
0x02C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
TXDATA
This frame will be added to the transmit buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared.
Reserved
SIGF
Set when a signal frame is detected.
STARTF
Set when a start frame is detected.
MPAF
Set when a multi-processor address frame is detected.
FERR
Set when a frame with a framing error is received while RXBLOCK is cleared.
PERR
Set when a frame with a parity error is received while RXBLOCK is cleared.
TXOF
Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.
RXUF
Set when trying to read from the receive buffer when it is empty.
RXOF
Set when data is incoming while the receive shift register is full. The data previously in shift register is overwritten by the new data.
RXDATAV
Set when data becomes available in the receive buffer.
TXBL
Set when space becomes available in the transmit buffer for a new frame.
Name
Name
0x00
0
0
0
0
0
0
0
0
0
1
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W
R
R
R
R
R
R
R
R
R
R
Access
Access
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236
Bit Position
Bit Position
TX Data
Signal Frame Interrupt Flag
Start Frame Interrupt Flag
Multi-Processor Address Frame Interrupt Flag
Framing Error Interrupt Flag
Parity Error Interrupt Flag
TX Overflow Interrupt Flag
RX Underflow Interrupt Flag
RX Overflow Interrupt Flag
RX Data Valid Interrupt Flag
TX Buffer Level Interrupt Flag
Description
Description
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