EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 352

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.5.4 ADCn_SINGLECTRL - Single Sample Control Register
8
7:2
1
0
31
30:28
27:25
24
23:20
Bit
Offset
0x00C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reference selected for scan mode is warmed up.
SINGLEREFWARM
Reference selected for single mode is warmed up.
Reserved
SCANACT
Scan sequence is active or has pending conversions.
SINGLEACT
Single conversion is active or has pending conversions.
Reserved
PRSSEL
Select PRS trigger for single sample.
Reserved
PRSEN
Enabled/disable PRS trigger of single sample.
AT
Select the acquisition time for single sample.
Name
Name
Value
0
1
2
3
4
5
6
7
Value
0
1
Value
0
1
2
3
4
5
6
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
Mode
1CYCLE
2CYCLES
4CYCLES
8CYCLES
16CYCLES
32CYCLES
64CYCLES
Description
Single sample is not triggered by PRS input
Single sample is triggered by PRS input selected by PRSSEL
0
0
0
0x0
0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
RW
RW
RW
Access
Access
Description
PRS ch 0 triggers single sample
PRS ch 1 triggers single sample
PRS ch 2 triggers single sample
PRS ch 3 triggers single sample
PRS ch 4 triggers single sample
PRS ch 5 triggers single sample
PRS ch 6 triggers single sample
PRS ch 7 triggers single sample
Description
1 ADC_CLK cycle acquisition time for single sample
2 ADC_CLK cycles acquisition time for single sample
4 ADC_CLK cycles acquisition time for single sample
8 ADC_CLK cycles acquisition time for single sample
16 ADC_CLK cycles acquisition time for single sample
32 ADC_CLK cycles acquisition time for single sample
64 ADC_CLK cycles acquisition time for single sample
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352
Bit Position
Single Reference Warmed Up
Scan Conversion Active
Single Conversion Active
Single Sample PRS Trigger Select
Single Sample PRS Trigger Enable
Single Sample Acquisition Time
Description
Description
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