EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 237

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.13 LEUARTn_IFS - Interrupt Flag Set Register
18.5.14 LEUARTn_IFC - Interrupt Flag Clear Register
0
31:11
10
9
8
7
6
5
4
3
2:1
0
Bit
Offset
0x030
Reset
Access
Name
Bit
Offset
0x034
Reset
Access
Name
2010-09-06 - d0001_Rev1.00
TXC
Set after a transmission when both the TX buffer and shift register are empty.
Reserved
SIGF
Write to 1 to set the SIGF interrupt flag.
STARTF
Write to 1 to set the STARTF interrupt flag.
MPAF
Write to 1 to set the MPAF interrupt flag.
FERR
Write to 1 to set the FERR interrupt flag.
PERR
Write to 1 to set the PERR interrupt flag.
TXOF
Write to 1 to set the TXOF interrupt flag.
RXUF
Write to 1 to set the RXUF interrupt flag.
RXOF
Write to 1 to set the RXOF interrupt flag.
Reserved
TXC
Write to 1 to set the TXC interrupt flag.
Name
Name
0
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
W1
W1
W1
W1
W1
W1
W1
W1
W1
Access
Access
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237
Bit Position
Bit Position
TX Complete Interrupt Flag
Set Signal Frame Interrupt Flag
Set Start Frame Interrupt Flag
Set Multi-Processor Address Frame Interrupt Flag
Set Framing Error Interrupt Flag
Set Parity Error Interrupt Flag
Set TX Overflow Interrupt Flag
Set RX Underflow Interrupt Flag
Set RX Overflow Interrupt Flag
Set TX Complete Interrupt Flag
Description
Description
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