EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 222

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.3.4.3 Jitter in Transmitted Data
18.3.5 Data Reception
18.3.5.1 Receive Buffer Operation
2010-09-06 - d0001_Rev1.00
Internally the LEUART module uses only the positive edges of the 32.768 kHz clock (LFBCLK) for
transmission and reception. Transmitted data will thus have jitter equal to the difference between the
optimal data set-up location and the closest positive edge on the 32.768 kHz clock. The jitter in on the
location data is set up by the transmitter will thus be no more than half a clock period according to the
optimal set-up location. The jitter in the period of a single baud output by the transmitter will never be
more than one clock period.
Data reception is enabled by setting RXEN in LEUARTn_CMD. When the receiver is enabled, it actively
samples the input looking for a transition from high to low indicating the start baud of a new frame. When
a start baud is found, reception of the new frame begins if the receive shift register is empty and ready
for new data. When the frame has been received, it is pushed into the receive buffer, making the shift
register ready for another frame of data, and the receiver starts looking for another start baud. If the
receive buffer is full, the received frame remains in the shift register until more space in the receive
buffer is available.
If an incoming frame is detected while both the receive buffer and the receive shift register are full, the
data in the receive shift register is overwritten, and the RXOF interrupt flag in LEUARTn_IF is set to
indicate the buffer overflow.
The receiver can be disabled by setting the command bit RXDIS in LEUARTn_CMD. Any frame currently
being received when the receiver is disabled is discarded. Whether or not the receiver is enabled at a
given time can be read out from RXENS in LEUARTn_STATUS.
When data becomes available in the receive buffer, the RXDATAV flag in LEUARTn_STATUS and the
RXDATAV interrupt flag in LEUARTn_IF are set. Both the RXDATAV status flag and the RXDATAV
interrupt flag are cleared by hardware when data is no longer available, i.e. when data has been read
out of the buffer.
Data can be read from receive buffer using either LEUARTn_RXDATA or LEUARTn_RXDATAX.
LEUARTn_RXDATA gives access to the 8 least significant bits of the received frame, while
LEUARTn_RXDATAX must be used to get access to the 9th, most significant bit. The latter register also
contains status information regarding the frame.
When a frame is read from the receive buffer using LEUARTn_RXDATA or LEUARTn_RXDATAX, the
frame is removed from the buffer, making room for a new one. If an attempt is done to read more
frames from the buffer than what is available, the RXUF interrupt flag in LEUARTn_IF is set to signal
the underflow, and the data read from the buffer is undefined.
Frames can also be read from the receive buffer without removing the data by using
LEUARTn_RXDATAXP, which gives access to the frame in the buffer including control bits. Data read
from this register when the receive buffer is empty is undefined. No underflow interrupt is generated
by a read using LEUARTn_RXDATAXP, i.e. the RXUF interrupt flag is never set as a result of reading
from LEUARTn_RXDATAXP.
An overview of the operation of the receiver is shown in Figure 18.4 (p. 223) .
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