EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 150

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.7.2 Interactions
2010-09-06 - d0001_Rev1.00
Whenever the I
all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software
depends on the current state the of the I
As an example, Table 15.4 (p. 152) shows the different states the I
as a Master Transmitter, i.e. a master that transmits data to a slave. As seen in the table, when a start
condition has been transmitted, a requirement is that there is an address and an R/W bit in the transmit
buffer. If the transmit buffer is empty, then the BUSHOLD interrupt flag is set, and the bus is held until
data becomes available in the buffer. While waiting for the address, I2Cn_STATE has a value 0x57,
which can be used to identify exactly what the I
Note
The different interactions used by the I
a set of different courses of action are possible from a given state, the course of action using the highest
priority interactions, that first has everything it is waiting for is the one that is taken.
Table 15.3. I
The commands marked with a * in Table 15.3 (p. 150) can be issued before an interaction is required.
When such a command is issued before it can be used/consumed by the I
Interaction
STOP*
ABORT
CONT*
NACK*
ACK*
ADDR+W -> TXDATA
ADDR+R -> TXDATA
START*
TXDATA
RXDATA
None
The bus would never stop at state 0x57 if the address was available in the transmit buffer.
2
C Interactions in Prioritized Order
2
C module is waiting for interaction from software, it holds the bus clock SCL low, freezing
Priority
1
2
3
4
5
6
7
8
9
10
11
2
2
C module are listed in Table 15.3 (p. 150) in prioritized order. If
C module. This state can be read from the I2Cn_STATE register.
2
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C module is waiting for.
150
Software action
Set the STOP command bit
in I2Cn_CMD
Set the ABORT command bit
in I2Cn_CMD
Set the CONT command bit
in I2Cn_CMD
Set the NACK command bit
in I2Cn_CMD
Set the ACK command bit in
I2Cn_CMD
Write an address to the
transmit buffer with the R/W
bit set
Write an address to the
transmit buffer with the R/W
bit cleared
Set the START command bit
in I2Cn_CMD
Write data to the transmit
buffer
Read data from receive
buffer
No interaction is required
2
C goes through when operating
2
C module, the command is
Automatically continues if
PSTOP is set (STOP
pending) in I2Cn_STATUS
Never, the transmission is
aborted
PCONT is set in
I2Cn_STATUS (CONT
pending)
PNACK is set in
I2Cn_STATUS (NACK
pending)
AUTOACK is set in
I2Cn_CTRL or PACK is
set in I2Cn_STATUS (ACK
pending)
Address is available in
transmit buffer with R/W bit
set
Address is available in
transmit buffer with R/W bit
cleared
PSTART is set in
I2Cn_STATUS (START
pending)
Data is available in transmit
buffer
Space is available in receive
buffer
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