EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 305

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.5.13 LETIMERn_FREEZE - Freeze Register
21.5.14 LETIMERn_SYNCBUSY - Synchronization Busy Register
2
1
0
31:1
0
31:6
5
4
3
2
Bit
Offset
0x030
Reset
Access
Name
Bit
Offset
0x034
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
UF
Set to enable interrupt on the UF interrupt flag.
COMP1
Set to enable interrupt on the COMP1 interrupt flag.
COMP0
Set to enable interrupt on the COMP0 interrupt flag.
Reserved
REGFREEZE
When set, the update of the LETIMER is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Reserved
REP1
Set when the value written to LETIMERn_REP1 is being synchronized.
REP0
Set when the value written to LETIMERn_REP0 is being synchronized.
COMP1
Set when the value written to LETIMERn_COMP1 is being synchronized.
COMP0
Name
Name
Name
Value
0
1
Mode
UPDATE
FREEZE
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
R
R
R
R
Access
Access
Access
Description
Each write access to a LETIMER register is updated into the Low Frequency domain
as soon as possible.
The LETIMER is not updated with the new written value.
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305
Bit Position
Bit Position
Underflow Interrupt Enable
Compare Match 1 Interrupt Enable
Compare Match 0 Interrupt Enable
Register Update Freeze
LETIMERn_REP1 Register Busy
LETIMERn_REP0 Register Busy
LETIMERn_COMP1 Register Busy
LETIMERn_COMP0 Register Busy
Description
Description
Description
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