EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 304

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.5.11 LETIMERn_IFC - Interrupt Flag Clear Register
21.5.12 LETIMERn_IEN - Interrupt Enable Register
1
0
31:5
4
3
2
1
0
31:5
4
3
Bit
Offset
0x028
Reset
Access
Name
Bit
Offset
0x02C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
COMP1
Write to 1 to set the COMP1 interrupt flag.
COMP0
Write to 1 to set the COMP0 interrupt flag.
Reserved
REP1
Write to 1 to clear the REP1 interrupt flag.
REP0
Write to 1 to clear the REP0 interrupt flag.
UF
Write to 1 to clear the UF interrupt flag.
COMP1
Write to 1 to clear the COMP1 interrupt flag.
COMP0
Write to 1 to clear the COMP0 interrupt flag.
Reserved
REP1
Set to enable interrupt on the REP1 interrupt flag.
REP0
Set to enable interrupt on the REP0 interrupt flag.
Name
Name
Name
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
W1
RW
RW
Access
Access
Access
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304
Bit Position
Bit Position
Set Compare Match 1 Interrupt Flag
Set Compare Match 0 Interrupt Flag
Clear Repeat Counter 1 Interrupt Flag
Clear Repeat Counter 0 Interrupt Flag
Clear Underflow Interrupt Flag
Clear Compare Match 1 Interrupt Flag
Clear Compare Match 0 Interrupt Flag
Repeat Counter 1 Interrupt Enable
Repeat Counter 0 Interrupt Enable
Description
Description
Description
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